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authorCaveh Jalali <caveh@chromium.org>2020-07-31 04:30:24 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-24 09:20:38 +0000
commit028e527cbd880078bc195fbf62e49732c7523904 (patch)
tree1957b8bc8f0689fc7436538c91a0349c2f1edbba /.checkpatch.conf
parenta360aad2bc8a70e9d11047f6ca03e65c9318dfb7 (diff)
downloadcoreboot-028e527cbd880078bc195fbf62e49732c7523904.tar.xz
mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table
GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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