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authorDuncan Laurie <dlaurie@google.com>2019-06-13 10:46:54 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-06-13 21:13:58 +0000
commitde666dc9b86452d5efbda70aa2364877d2fcd449 (patch)
tree2362885ae75cb63d83dfb2ad0880ad2bc2d3ad5c /.checkpatch.conf
parent7945f7541717f07c038a0fa4c38130bb1128e2d8 (diff)
downloadcoreboot-de666dc9b86452d5efbda70aa2364877d2fcd449.tar.xz
mb/google/sarien: Disable unused GPIOs
These 4 GPIOs are being disconnected in the next board so use the board ID to configure these pins as not connected to ensure they do not cause leakage. Also remove the ACPI _PTS S5 code that was configuring the GPIOs. This does mean they will cause small leakage in S5 on existing boards, but it will not affect the new boards. BUG=b:132393441 TEST=boot on sarien with fake board ID and ensure that coreboot configures these pads as expected. Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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