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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2018-08-23 14:48:06 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2018-08-27 06:31:27 +0000 |
| commit | 56508967d8b433b2821d54207370332e1f319354 (patch) | |
| tree | 136e5408a17b0d396a659a421f070fa24e5a54b5 /.clang-format | |
| parent | c5cca15cce060699256cb7f81aeefb39065ac3bd (diff) | |
| download | coreboot-56508967d8b433b2821d54207370332e1f319354.tar.xz | |
siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
This patch disables the unused PCI clock outputs on the XIO2001 PCI
Express to PCI Bridge.
Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to '.clang-format')
0 files changed, 0 insertions, 0 deletions