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| author | Duncan Laurie <dlaurie@google.com> | 2018-12-10 11:19:36 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-14 18:30:15 +0000 |
| commit | 28e8ae5385668bb7c26666c0a0bf0208231da78f (patch) | |
| tree | 32f7cc62c9eb2a867c266d1255a0debb21448a5e /.clang-format | |
| parent | 1c88cd6c2b70287589498686786038b774cdab61 (diff) | |
| download | coreboot-28e8ae5385668bb7c26666c0a0bf0208231da78f.tar.xz | |
soc/intel/common: Add support for GPIO group pad base
In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.
To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.
By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.
BUG=b:120686247
TEST=tested on a sarien(cannonlake) board
Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to '.clang-format')
0 files changed, 0 insertions, 0 deletions