summaryrefslogtreecommitdiff
path: root/.gitignore
diff options
context:
space:
mode:
authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-02-19 00:48:55 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-26 17:08:36 +0000
commitfdba0cd6af05f9317dbd19956d644ce01e37a547 (patch)
treeddaedb4aef31acee0af965c0382128dea5e517fa /.gitignore
parent1f9112f798c127fc9fa50f6f927dcea84baa1845 (diff)
downloadcoreboot-fdba0cd6af05f9317dbd19956d644ce01e37a547.tar.xz
mb/intel/tglrvp: add Tiger Lake memory initialization support
Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions