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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-03-05 16:40:07 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:26:04 +0200 |
| commit | 59074ff89fee709a3822d50a400834b70dd87b23 (patch) | |
| tree | 0ad66dd2353dd2185be1c3d384667b8918f4a643 /.gitmodules | |
| parent | 1e935bf4e21a1faf563f3700246fcc40f4294ca7 (diff) | |
| download | coreboot-59074ff89fee709a3822d50a400834b70dd87b23.tar.xz | |
pistachio: clean DDR2 initialization code
The proper way to initialize DDR2 is for the PHY to
automatically establish precise timing configuration
through the training process. The alternative (used
initially for testing) is no longer needed.
This change determined the removal of some local
variables as they ended up being used in one location only.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly.
BRANCH=none
Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e28f3ef9a22436bb0fa949df6f5a5c6a67002dfd
Original-Change-Id: Ifb9c1bb6e0b71af72340381bd2349850d1b4af2d
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256303
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to '.gitmodules')
0 files changed, 0 insertions, 0 deletions