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| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-07 14:02:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 16:38:42 +0200 |
| commit | 03e971cd23e96b9293fc3ecc420f56ad91326cd9 (patch) | |
| tree | 722243549211ec6204f190f1d2c1d825d41aa466 /.gitreview | |
| parent | 0637e567e13adab5b204a33fc57a54f437761f3f (diff) | |
| download | coreboot-03e971cd23e96b9293fc3ecc420f56ad91326cd9.tar.xz | |
soc/intel/common/block: Add cache as ram init and teardown code
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions