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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-07-26 01:54:34 +0200
committerMartin Roth <martinroth@google.com>2016-08-02 23:35:49 +0200
commitcc5be8b72ba5b072030fdd1d382d7156da43114f (patch)
treecb94bc583e87b6c58bdf675fdec363003d316227 /.gitreview
parentaded214e74bcb63990d69551bec7ab03c6785b08 (diff)
downloadcoreboot-cc5be8b72ba5b072030fdd1d382d7156da43114f.tar.xz
arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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