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| author | Furquan Shaikh <furquan@google.com> | 2020-05-16 21:46:41 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-20 00:35:25 +0000 |
| commit | 66b9c0efb52f8953e52add59c70646fa1ce1b867 (patch) | |
| tree | b3f57be5af34e0a99cbe84e2e43070bb0bf5eea5 /.gitreview | |
| parent | 6dc858a01ffceb897b597607f2004b9aad2f0ae7 (diff) | |
| download | coreboot-66b9c0efb52f8953e52add59c70646fa1ce1b867.tar.xz | |
soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions