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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-02-25 23:20:14 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-26 20:05:16 +0100 |
| commit | ba894be382c1a0365c435d5be2b54422731d66c8 (patch) | |
| tree | 73678d140d2ed454976028c451c8ed4c3b0ca5ff /.gitreview | |
| parent | d912f1d4f973f415a431932b71e9cee0b1c82549 (diff) | |
| download | coreboot-ba894be382c1a0365c435d5be2b54422731d66c8.tar.xz | |
During DRAM initialization on certain ASpeed devices, an incorrect
bit (bit 10) was checked in the "SDRAM Bus Width Status" register
to determine DRAM width.
Query bit 6 instead in accordance with the Aspeed AST2050 datasheet
v1.05.
Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13807
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions