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| author | Furquan Shaikh <furquan@google.com> | 2020-05-04 22:54:22 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-12 20:05:43 +0000 |
| commit | dd5264612ae8145c8c8e38d2ff3fb7e47de8e4b2 (patch) | |
| tree | bf67f00d4c4aade3a97b06e0d277ecde3ef18af7 /.gitreview | |
| parent | 5cc41f2a6b6aeca1500fe9f55af5858d1c7e4e38 (diff) | |
| download | coreboot-dd5264612ae8145c8c8e38d2ff3fb7e47de8e4b2.tar.xz | |
soc/amd/common/block: Add header file for eSPI register definitions
This change adds eSPI register definitions for I/O and MMIO decode
using eSPI on AMD SoCs. Additionally, it also adds a macro to define
the offset of ESPI MMIO base from SPI MMIO base.
BUG=b:153675913
Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to '.gitreview')
0 files changed, 0 insertions, 0 deletions