summaryrefslogtreecommitdiff
path: root/3rdparty/chromeec
diff options
context:
space:
mode:
authorMike Loptien <mike.loptien@se-eng.com>2013-03-13 16:28:16 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-13 23:44:00 +0100
commit7bc153c6aef0f2615e3dadb274b9fed56ed15732 (patch)
tree3e40f1f91fdbc22ab8e5eb52a3e83fdbe514e346 /3rdparty/chromeec
parent00e5da6f25483f5d29aefadfff56a11dd0f3c97c (diff)
downloadcoreboot-7bc153c6aef0f2615e3dadb274b9fed56ed15732.tar.xz
Eagleheights DSDT: Grant OS control through OSC
Change the OSC method to actually grant control of PCIe capabilities to the OS instead of granting no control. I believe the logic was backwards in the original commit. Bits should be set when granting control and cleared when not granting control. By setting the return value to 0x00, we effectively tell the OS that it cannot control any PCIe capability. See section 6.2.9 of the ACPI spec version 3.0 for more information. This edit is a duplication of the OSC method that is in the src/southbridge/intel/bd82x6x/pch.asl file. Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2714 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to '3rdparty/chromeec')
m---------3rdparty0
1 files changed, 0 insertions, 0 deletions
diff --git a/3rdparty b/3rdparty
-Subproject ba8caa30bd5ed6d89dbfd40e17c75c94d43804c
+Subproject dac1a18d184976e4447b98479f0b7a172054b98