diff options
author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-02-13 14:24:16 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-11 15:03:39 +0000 |
commit | cb858d6d6287d0e5e15583a1ff53f77ffea730bc (patch) | |
tree | 6862fc43b00d25e1e396f1194c158c9971512102 /3rdparty/chromeec | |
parent | 6dc488a6781e4b0ecd0d4cb963d40709f17df0ef (diff) | |
download | coreboot-cb858d6d6287d0e5e15583a1ff53f77ffea730bc.tar.xz |
superio/nuvoton/nct5539d: Update documentation and remove DSDT
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to '3rdparty/chromeec')
0 files changed, 0 insertions, 0 deletions