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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-10-04 11:49:29 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-08-31 23:53:15 +0200 |
| commit | 598bf954e9050a1bf9cb77e647ca7e9fb44bef44 (patch) | |
| tree | daa6f23a14d88aaff2f8c322bfa29a6916f807c3 /3rdparty/intel-sec-tools | |
| parent | 49ba28339087cb1057fbb12071a0981013a88e55 (diff) | |
| download | coreboot-598bf954e9050a1bf9cb77e647ca7e9fb44bef44.tar.xz | |
samus: Change SPD to indicate LPDDR
There is some magic new SPD SDRAM type 241 to indicate LPDDR.
I cannot find it specificed in any JEDEC document but it is
what the reference code uses.
Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6777
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to '3rdparty/intel-sec-tools')
0 files changed, 0 insertions, 0 deletions