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| author | Martin Roth <martinroth@chromium.org> | 2019-12-16 23:21:05 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-03-17 22:47:20 +0000 |
| commit | 4017de0d10d4b464ec14663dfd0c8bd1cbcfba20 (patch) | |
| tree | f06be4e519a905bc4979fe5d1c2e132c98925a8d /3rdparty/opensbi | |
| parent | ba37b94e8e7819913a53b62143ee1e7fb897592e (diff) | |
| download | coreboot-4017de0d10d4b464ec14663dfd0c8bd1cbcfba20.tar.xz | |
soc/amd/picasso: Set I2C clock reference to 150MHz
Picasso uses a 150MHz reference clock for the Designware I2C devices.
This update allows us to get the correct speeds out.
BUG=b:143885765
TEST=Trembyle has 400kHz I2C clock
Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1970656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to '3rdparty/opensbi')
0 files changed, 0 insertions, 0 deletions