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authorVince Hsu <vinceh@nvidia.com>2014-06-11 17:14:05 +0800
committerMarc Jones <marc.jones@se-eng.com>2015-01-04 00:14:03 +0100
commit1e3679ddd0fd03fdc00b50a45fc652a539b9c9a7 (patch)
tree11020367ea7d724801654a7e3f7b017048b393ce /3rdparty
parentc1f7cbe49f0023655f6f60b1d924ed5c61533806 (diff)
downloadcoreboot-1e3679ddd0fd03fdc00b50a45fc652a539b9c9a7.tar.xz
tegra124: configure DP with correct pixel clock
For some panels, the plld can't provide the pixel clock that the panels wants, so we give it a good enough one. And we should calculate the dp/dc settings by the real pixel clock. BRANCH=nyan BUG=chrome-os-partner:29489 TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big). No screen flicker is observed. No sor dp fifo underflow found. Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779 Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203358 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac Reviewed-on: http://review.coreboot.org/8044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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