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author | Aaron Durbin <adurbin@chromium.org> | 2016-05-26 10:55:48 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-27 19:53:16 +0200 |
commit | 10221a0e570717760087163b075f7f535f882b61 (patch) | |
tree | e93c66d9ad1a4ffec1e3ef951c9cb51893743391 /3rdparty | |
parent | a9ac2d9b914d849b207d3f6c73892240017bf932 (diff) | |
download | coreboot-10221a0e570717760087163b075f7f535f882b61.tar.xz |
arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK
When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for
a chipset specific verstage entry point because cache-as-ram has
already been initialized. Therefore, provide a default entry point
for verstage in that environment.
Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14971
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to '3rdparty')
0 files changed, 0 insertions, 0 deletions