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authorGabe Black <gabeblack@google.com>2014-03-05 22:24:54 -0800
committerMarc Jones <marc.jones@se-eng.com>2014-11-13 06:27:50 +0100
commit1f4e283560cd621372b0b48f5a20d5ddb4c01b80 (patch)
treee2e9a6e42bef89c61a3dc82205dfd18162e3c468 /3rdparty
parent41c926029c4fb80f8c3d103681f4e9434ca9677c (diff)
downloadcoreboot-1f4e283560cd621372b0b48f5a20d5ddb4c01b80.tar.xz
nyan: big: Only delay when and as long as necessary in the PMIC setup code.
The PMIC setup code was unconditionally waiting for 10ms after each register write. It might be possible for there to be an excess of current from lots of rails switching around at the same time, but we can avoid that with a much shorter delay in a few strategic places. This change also moves the write to LDO3 to just under SD1 because LDO3 should track SD1. The duration and position for the delays and moving LDO3 were provided by Dan Coggin at nvidia. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Measured a 230 ms decrease in boot time. BRANCH=None Original-Change-Id: I14805bf1b6242bdd0b286f37ae7d635c03909677 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189016 Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Daniel Coggin <dcoggin@nvidia.com> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 06c4d346deeb47809cd88655a9fa6712ceef9491) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3ce0bdeb4ee60499f6c192fe0803a4cab3d7a8af Reviewed-on: http://review.coreboot.org/7419 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
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