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authorFrans Hendriks <fhendriks@eltan.com>2018-12-12 08:13:30 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 10:07:38 +0000
commit0556f6132b28ff8da45a5a1b4ef4c66e95b5bcb9 (patch)
treeca2d8a846367bf72394644a7f7e237db7727a5f1
parent34564ed154b6734cc51bf05d61b45d9a74cdc2b5 (diff)
downloadcoreboot-0556f6132b28ff8da45a5a1b4ef4c66e95b5bcb9.tar.xz
soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
Linux remains using SPI1 and PWM ASL even if these devices are disabled. SPI1 and PWM are disabled by Intel FSP. Remove ASL code. BUG=N/A TEST=Boot Ubuntu on Intel CherryHill CRB Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
-rw-r--r--src/soc/intel/braswell/acpi/lpss.asl110
1 files changed, 1 insertions, 109 deletions
diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl
index 4cc93cc2d2..f9b376ccb3 100644
--- a/src/soc/intel/braswell/acpi/lpss.asl
+++ b/src/soc/intel/braswell/acpi/lpss.asl
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -522,115 +523,6 @@ Device (I2C7)
}
}
-Device (SPI1)
-{
- Name (_HID, "8086228E")
- Name (_UID, 1)
- Name (_DDN, "SPI Controller #2")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- LPSS_SPI_IRQ
- }
- FixedDMA (0x0, 0x0, Width32Bit, )
- FixedDMA (0x1, 0x1, Width32Bit, )
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\S9B0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\S9EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- OperationRegion (KEYS, SystemMemory, S9B1, 0x100)
- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
- {
- Offset (0x84),
- PSAT, 32,
- }
-
- Method (_PS3)
- {
- Or (PSAT, 0x00000003, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-
- Method (_PS0)
- {
- And (PSAT, 0xfffffffc, PSAT)
- Or (PSAT, 0x00000000, PSAT)
- }
-}
-
-Device (PWM1)
-{
- Name (_HID, "80862288")
- Name (_UID, 1)
- Name (_DDN, "PWM Controller #1")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\SAB0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\SAEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-}
-
-Device (PWM2)
-{
- Name (_HID, "80862288")
- Name (_UID, 2)
- Name (_DDN, "PWM Controller #2")
-
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- })
-
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
- Store (\SBB0, RBAS)
- Return (^RBUF)
- }
-
- Method (_STA)
- {
- If (LEqual (\SBEN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-}
-
Device (UAR1)
{
Name (_HID, "8086228A")