summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorefdesign98 <efdesign98@gmail.com>2011-06-20 17:38:49 -0700
committerMarc Jones <marcj303@gmail.com>2011-06-22 01:27:46 +0200
commit05a89ab922473f375820a3bd68691bb085c62448 (patch)
tree22510d53ab35d80987cb17f2a11ce08039db49a5
parentee39ea7e7edf9699f1bae1b2708ad6816f054817 (diff)
downloadcoreboot-05a89ab922473f375820a3bd68691bb085c62448.tar.xz
Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
-rw-r--r--src/cpu/amd/Kconfig2
-rw-r--r--src/cpu/amd/Makefile.inc2
-rw-r--r--src/cpu/amd/agesa/Kconfig (renamed from src/cpu/amd/agesa_wrapper/Kconfig)2
-rw-r--r--src/cpu/amd/agesa/Makefile.inc (renamed from src/cpu/amd/agesa_wrapper/Makefile.inc)2
-rw-r--r--src/cpu/amd/agesa/family14/Kconfig (renamed from src/cpu/amd/agesa_wrapper/family14/Kconfig)26
-rw-r--r--src/cpu/amd/agesa/family14/Makefile.inc (renamed from src/cpu/amd/agesa_wrapper/family14/Makefile.inc)4
-rw-r--r--src/cpu/amd/agesa/family14/apic_timer.c (renamed from src/cpu/amd/agesa_wrapper/family14/apic_timer.c)0
-rw-r--r--src/cpu/amd/agesa/family14/cache_as_ram.inc (renamed from src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc)0
-rw-r--r--src/cpu/amd/agesa/family14/chip.h (renamed from src/northbridge/amd/agesa_wrapper/family14/chip.h)7
-rw-r--r--src/cpu/amd/agesa/family14/chip_name.c (renamed from src/cpu/amd/agesa_wrapper/family14/chip_name.c)2
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c (renamed from src/cpu/amd/agesa_wrapper/family14/model_14_init.c)0
-rw-r--r--src/mainboard/advansus/a785e-i/Kconfig2
-rw-r--r--src/mainboard/advansus/a785e-i/devicetree.cb4
-rw-r--r--src/mainboard/advansus/a785e-i/romstage.c2
-rw-r--r--src/mainboard/amd/inagua/Kconfig8
-rw-r--r--src/mainboard/amd/inagua/devicetree.cb18
-rw-r--r--src/mainboard/amd/persimmon/Kconfig8
-rw-r--r--src/mainboard/amd/persimmon/devicetree.cb18
-rw-r--r--src/mainboard/asrock/e350m1/Kconfig8
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb18
-rw-r--r--src/northbridge/amd/Kconfig2
-rw-r--r--src/northbridge/amd/Makefile.inc2
-rw-r--r--src/northbridge/amd/agesa/Kconfig (renamed from src/southbridge/amd/cimx_wrapper/Kconfig)3
-rw-r--r--src/northbridge/amd/agesa/Makefile.inc19
-rw-r--r--src/northbridge/amd/agesa/family14/Kconfig (renamed from src/northbridge/amd/agesa_wrapper/family14/Kconfig)8
-rw-r--r--src/northbridge/amd/agesa/family14/Makefile.inc (renamed from src/northbridge/amd/agesa_wrapper/family14/Makefile.inc)0
-rw-r--r--src/northbridge/amd/agesa/family14/amdfam14_conf.c (renamed from src/northbridge/amd/agesa_wrapper/family14/amdfam14_conf.c)0
-rw-r--r--src/northbridge/amd/agesa/family14/bootblock.c (renamed from src/northbridge/amd/agesa_wrapper/family14/bootblock.c)0
-rw-r--r--src/northbridge/amd/agesa/family14/chip.h (renamed from src/cpu/amd/agesa_wrapper/family14/chip.h)7
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c (renamed from src/northbridge/amd/agesa_wrapper/family14/northbridge.c)16
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.h (renamed from src/northbridge/amd/agesa_wrapper/family14/northbridge.h)6
-rw-r--r--src/northbridge/amd/agesa/family14/root_complex/Kconfig2
-rw-r--r--src/northbridge/amd/agesa/family14/root_complex/chip.h24
-rw-r--r--src/northbridge/amd/agesa/family14/ssdt.asl (renamed from src/northbridge/amd/agesa_wrapper/family14/ssdt.asl)0
-rw-r--r--src/northbridge/amd/agesa_wrapper/Makefile.inc19
-rw-r--r--src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig2
-rw-r--r--src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h24
-rw-r--r--src/southbridge/amd/Kconfig2
-rw-r--r--src/southbridge/amd/Makefile.inc2
-rw-r--r--src/southbridge/amd/cimx/Kconfig (renamed from src/northbridge/amd/agesa_wrapper/Kconfig)3
-rw-r--r--src/southbridge/amd/cimx/Makefile.inc19
-rw-r--r--src/southbridge/amd/cimx/sb800/Amd.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/Amd.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/AmdSbLib.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/AmdSbLib.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/Kconfig (renamed from src/southbridge/amd/cimx_wrapper/sb800/Kconfig)8
-rw-r--r--src/southbridge/amd/cimx/sb800/Makefile.inc (renamed from src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc)0
-rw-r--r--src/southbridge/amd/cimx/sb800/SBPLATFORM.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/SbEarly.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/bootblock.c)0
-rw-r--r--src/southbridge/amd/cimx/sb800/cbtypes.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/cfg.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/cfg.c)0
-rw-r--r--src/southbridge/amd/cimx/sb800/cfg.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/cfg.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/chip.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/chip.h)10
-rw-r--r--src/southbridge/amd/cimx/sb800/chip_name.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/chip_name.c)2
-rw-r--r--src/southbridge/amd/cimx/sb800/early.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/early.c)0
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/late.c)8
-rw-r--r--src/southbridge/amd/cimx/sb800/lpc.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/lpc.c)0
-rw-r--r--src/southbridge/amd/cimx/sb800/lpc.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/lpc.h)0
-rw-r--r--src/southbridge/amd/cimx/sb800/smbus.c (renamed from src/southbridge/amd/cimx_wrapper/sb800/smbus.c)0
-rw-r--r--src/southbridge/amd/cimx/sb800/smbus.h (renamed from src/southbridge/amd/cimx_wrapper/sb800/smbus.h)0
-rw-r--r--src/southbridge/amd/cimx_wrapper/Makefile.inc19
-rw-r--r--src/vendorcode/amd/agesa/Lib/amdlib.c42
-rw-r--r--src/vendorcode/amd/cimx/sb800/Makefile.inc2
62 files changed, 192 insertions, 192 deletions
diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index 0e2683401c..2f4ff33aec 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -22,4 +22,4 @@ source src/cpu/amd/model_lx/Kconfig
source src/cpu/amd/sc520/Kconfig
-source src/cpu/amd/agesa_wrapper/Kconfig
+source src/cpu/amd/agesa/Kconfig
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 031e921a2b..dfa6d1ea2b 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -14,5 +14,5 @@ subdirs-$(CONFIG_CPU_AMD_LX) += model_lx
subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
-subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper
+subdirs-$(CONFIG_AMD_AGESA) += agesa
subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
diff --git a/src/cpu/amd/agesa_wrapper/Kconfig b/src/cpu/amd/agesa/Kconfig
index 513c06a116..2133f89f94 100644
--- a/src/cpu/amd/agesa_wrapper/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -17,4 +17,4 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-source src/cpu/amd/agesa_wrapper/family14/Kconfig
+source src/cpu/amd/agesa/family14/Kconfig
diff --git a/src/cpu/amd/agesa_wrapper/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 8780b8e673..222bcf917e 100644
--- a/src/cpu/amd/agesa_wrapper/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -16,4 +16,4 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-subdirs-$(CONFIG_CPU_AMD_AGESA_WRAPPER_FAMILY14) += family14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
diff --git a/src/cpu/amd/agesa_wrapper/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index ce633e00a3..8f3e766e6f 100644
--- a/src/cpu/amd/agesa_wrapper/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -17,58 +17,58 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-config CPU_AMD_AGESA_WRAPPER_FAMILY14
+config CPU_AMD_AGESA_FAMILY14
bool
select PCI_IO_CFG_EXT
config CPU_ADDR_BITS
int
default 36
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config CPU_SOCKET_TYPE
hex
default 0x10
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
# DDR2 and REG
config DIMM_SUPPORT
hex
default 0x0104
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config CBB
hex
default 0x0
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config CDB
hex
default 0x18
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config XIP_ROM_BASE
hex
default 0xfff80000
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
+ depends on CPU_AMD_AGESA_FAMILY14
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
-
+ depends on CPU_AMD_AGESA_FAMILY14
+
config HAVE_INIT_TIMER
bool
default y
- depends on CPU_AMD_AGESA_WRAPPER_FAMILY14
-
+ depends on CPU_AMD_AGESA_FAMILY14
+
diff --git a/src/cpu/amd/agesa_wrapper/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 59728b5584..ea6c51a1c3 100644
--- a/src/cpu/amd/agesa_wrapper/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -16,7 +16,7 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-
+
ramstage-y += chip_name.c
driver-y += model_14_init.c
@@ -279,4 +279,4 @@ subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm
ramstage-y += apic_timer.c
-cpu_incs += $(src)/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc
+cpu_incs += $(src)/cpu/amd/agesa/family14/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa_wrapper/family14/apic_timer.c b/src/cpu/amd/agesa/family14/apic_timer.c
index 26d3f88e49..26d3f88e49 100644
--- a/src/cpu/amd/agesa_wrapper/family14/apic_timer.c
+++ b/src/cpu/amd/agesa/family14/apic_timer.c
diff --git a/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc b/src/cpu/amd/agesa/family14/cache_as_ram.inc
index 98da3cbffb..98da3cbffb 100644
--- a/src/cpu/amd/agesa_wrapper/family14/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/family14/cache_as_ram.inc
diff --git a/src/northbridge/amd/agesa_wrapper/family14/chip.h b/src/cpu/amd/agesa/family14/chip.h
index 8319e98f56..d67184e306 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/chip.h
+++ b/src/cpu/amd/agesa/family14/chip.h
@@ -17,8 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-struct northbridge_amd_agesa_wrapper_family14_config
-{
-};
+extern struct chip_operations cpu_amd_agesa_family14_ops;
-extern struct chip_operations northbridge_amd_agesa_wrapper_family14_ops;
+struct cpu_amd_agesa_family14_config {
+};
diff --git a/src/cpu/amd/agesa_wrapper/family14/chip_name.c b/src/cpu/amd/agesa/family14/chip_name.c
index 1217ebc4f8..2c296f59d3 100644
--- a/src/cpu/amd/agesa_wrapper/family14/chip_name.c
+++ b/src/cpu/amd/agesa/family14/chip_name.c
@@ -20,6 +20,6 @@
#include <device/device.h>
#include "chip.h"
-struct chip_operations cpu_amd_agesa_wrapper_family14_ops = {
+struct chip_operations cpu_amd_agesa_family14_ops = {
CHIP_NAME("AMD CPU Family 14h")
};
diff --git a/src/cpu/amd/agesa_wrapper/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index c94e2150aa..c94e2150aa 100644
--- a/src/cpu/amd/agesa_wrapper/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig
index ab3104bdaa..6e3a4ab528 100644
--- a/src/mainboard/advansus/a785e-i/Kconfig
+++ b/src/mainboard/advansus/a785e-i/Kconfig
@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select QRANK_DIMM_SUPPORT
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
- select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+ select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_WINBOND_W83627HF #COM1, COM2
#select SUPERIO_FINTEK_F81216AD #COM3, COM4
select HAVE_BUS_CONFIG
diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb
index 74f50d02fa..25a1f646d8 100644
--- a/src/mainboard/advansus/a785e-i/devicetree.cb
+++ b/src/mainboard/advansus/a785e-i/devicetree.cb
@@ -34,7 +34,7 @@ chip northbridge/amd/amdfam10/root_complex
register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL
end
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pci bus
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
@@ -112,7 +112,7 @@ chip northbridge/amd/amdfam10/root_complex
#register "gpp_configuration" = "3" #2:1:1:0
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx_wrapper/sb800
+ end #southbridge/amd/cimx/sb800
end # device pci 18.0
device pci 18.1 on end
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index f2544e70ec..9e31779118 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -49,7 +49,7 @@
#include "southbridge/amd/rs780/early_setup.c"
#include <SbEarly.h>
#include <SBPLATFORM.h> /* SB OEM constants */
-#include <southbridge/amd/cimx_wrapper/sb800/smbus.h>
+#include <southbridge/amd/cimx/sb800/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 8e4eca96b5..eb43d6d59e 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -24,10 +24,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select ARCH_X86
select DIMM_DDR3
select DIMM_UNREGISTERED
- select CPU_AMD_AGESA_WRAPPER_FAMILY14
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
- select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+ select CPU_AMD_AGESA_FAMILY14
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14
+ select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_SMSC_KBC1100
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index acae2ca42b..67be34e8be 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -16,17 +16,17 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
device lapic_cluster 0 on
- chip cpu/amd/agesa_wrapper/family14
+ chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device pci_domain 0 on
subsystemid 0x1022 0x1510 inherit
- chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
- chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+ chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge
device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
- end # agesa_wrapper northbridge
+ end # agesa northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
@@ -73,7 +73,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 15.3 on end # PCIe PortD
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx_wrapper/sb800
+ end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pci 18.0 on end
@@ -85,7 +85,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
- end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 54db652c6a..034984c80f 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -22,10 +22,10 @@ if BOARD_AMD_PERSIMMON
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_AMD_AGESA_WRAPPER_FAMILY14
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
- select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+ select CPU_AMD_AGESA_FAMILY14
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14
+ select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_FINTEK_F81865F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 3a9ec400a6..a6763884c7 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -16,17 +16,17 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
device lapic_cluster 0 on
- chip cpu/amd/agesa_wrapper/family14
+ chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device pci_domain 0 on
subsystemid 0x1022 0x1510 inherit
- chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
- chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+ chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
- end # agesa_wrapper northbridge
+ end # agesa northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
@@ -89,7 +89,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 15.3 off end # PCIe PortD
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx_wrapper/sb800
+ end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pci 18.0 on end
@@ -101,7 +101,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
- end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index fdcc3c9ab3..e6153c01f2 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -22,10 +22,10 @@ if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_AMD_AGESA_WRAPPER_FAMILY14
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
- select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+ select CPU_AMD_AGESA_FAMILY14
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14
+ select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_WINBOND_W83627HF
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 43607ebb02..5983ed2148 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -16,17 +16,17 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
device lapic_cluster 0 on
- chip cpu/amd/agesa_wrapper/family14
+ chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device pci_domain 0 on
subsystemid 0x1022 0x1510 inherit
- chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
- chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+ chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
- end # agesa_wrapper northbridge
+ end # agesa northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
@@ -113,7 +113,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
register "gpp_configuration" = "4"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx_wrapper/sb800
+ end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pci 18.0 on end
@@ -125,7 +125,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
- end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig
index 914a3d2d5a..4a120ca50b 100644
--- a/src/northbridge/amd/Kconfig
+++ b/src/northbridge/amd/Kconfig
@@ -3,7 +3,7 @@ source src/northbridge/amd/gx1/Kconfig
source src/northbridge/amd/gx2/Kconfig
source src/northbridge/amd/amdfam10/Kconfig
source src/northbridge/amd/lx/Kconfig
-source src/northbridge/amd/agesa_wrapper/Kconfig
+source src/northbridge/amd/agesa/Kconfig
menu "HyperTransport setup"
#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index ba7027c8f3..328fd0f812 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -4,5 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1
subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
-subdirs-$(CONFIG_AMD_AGESA) += agesa_wrapper
+subdirs-$(CONFIG_AMD_AGESA) += agesa
subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
diff --git a/src/southbridge/amd/cimx_wrapper/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 2a51883ac2..8f282ecfb8 100644
--- a/src/southbridge/amd/cimx_wrapper/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -17,4 +17,5 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-source src/southbridge/amd/cimx_wrapper/sb800/Kconfig
+source src/northbridge/amd/agesa/family14/Kconfig
+
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
new file mode 100644
index 0000000000..eed0e05a41
--- /dev/null
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -0,0 +1,19 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
diff --git a/src/northbridge/amd/agesa_wrapper/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index ed4c5c7019..cdc207b01c 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -16,12 +16,12 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+config NORTHBRIDGE_AMD_AGESA_FAMILY14
bool
select MMCONF_SUPPORT
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
-if NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+if NORTHBRIDGE_AMD_AGESA_FAMILY14
config HW_MEM_HOLE_SIZEK
hex
@@ -41,6 +41,6 @@ config MMCONF_BUS_NUMBER
config BOOTBLOCK_NORTHBRIDGE_INIT
string
- default "northbridge/amd/agesa_wrapper/family14/bootblock.c"
+ default "northbridge/amd/agesa/family14/bootblock.c"
endif
diff --git a/src/northbridge/amd/agesa_wrapper/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 3bda8d5cc4..3bda8d5cc4 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
diff --git a/src/northbridge/amd/agesa_wrapper/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
index 6ec4da9c9f..6ec4da9c9f 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/amdfam14_conf.c
+++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c
diff --git a/src/northbridge/amd/agesa_wrapper/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
index eead31d26b..eead31d26b 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/bootblock.c
+++ b/src/northbridge/amd/agesa/family14/bootblock.c
diff --git a/src/cpu/amd/agesa_wrapper/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h
index d7c175361f..26a1aad6bb 100644
--- a/src/cpu/amd/agesa_wrapper/family14/chip.h
+++ b/src/northbridge/amd/agesa/family14/chip.h
@@ -17,7 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations cpu_amd_agesa_wrapper_family14_ops;
-
-struct cpu_amd_agesa_wrapper_family14_config {
+struct northbridge_amd_agesa_family14_config
+{
};
+
+extern struct chip_operations northbridge_amd_agesa_family14_ops;
diff --git a/src/northbridge/amd/agesa_wrapper/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index af7d1302d6..78ba2dad07 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -303,7 +303,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#if 0
- // We need to double check if there is speical set on base reg and limit reg
+ // We need to double check if there is speical set on base reg and limit reg
// are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) {
resource_t limitk_pri = 0;
@@ -324,7 +324,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
}
#endif
-
+
return mem_hole;
}
#endif
@@ -459,7 +459,7 @@ static void set_resources(device_t dev)
struct resource *res;
printk(BIOS_DEBUG, "\nFam14h - set_resources.\n");
-
+
/* Find the nodeid */
nodeid = amdfam14_nodeid(dev);
@@ -749,11 +749,11 @@ static void domain_enable_resources(device_t dev)
u32 val;
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n");
- val = agesawrapper_amdinitmid ();
+ val = agesawrapper_amdinitmid ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
}
-
+
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
}
@@ -785,7 +785,7 @@ static void cpu_bus_set_resources(device_t dev)
}
pci_dev_set_resources(dev);
}
-
+
static void cpu_bus_init(device_t dev)
{
struct device_path cpu_path;
@@ -826,7 +826,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
};
-struct chip_operations northbridge_amd_agesa_wrapper_family14_ops = {
+struct chip_operations northbridge_amd_agesa_family14_ops = {
CHIP_NAME("AMD Family 14h Northbridge")
.enable_dev = 0,
};
@@ -865,7 +865,7 @@ static void root_complex_enable_dev(struct device *dev)
}
-struct chip_operations northbridge_amd_agesa_wrapper_family14_root_complex_ops = {
+struct chip_operations northbridge_amd_agesa_family14_root_complex_ops = {
CHIP_NAME("AMD Family 14h Root Complex")
.enable_dev = root_complex_enable_dev,
};
diff --git a/src/northbridge/amd/agesa_wrapper/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h
index 2e9be562fc..fb8df38352 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/northbridge.h
+++ b/src/northbridge/amd/agesa/family14/northbridge.h
@@ -17,10 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H
-#define NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM14H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM14H_H
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
-#endif /* NORTHBRIDGE_AMD_AGESA_WRAPPER_FAM14H_H */
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */
diff --git a/src/northbridge/amd/agesa/family14/root_complex/Kconfig b/src/northbridge/amd/agesa/family14/root_complex/Kconfig
new file mode 100644
index 0000000000..f4eed4f2e1
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/root_complex/Kconfig
@@ -0,0 +1,2 @@
+config NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+ bool
diff --git a/src/northbridge/amd/agesa/family14/root_complex/chip.h b/src/northbridge/amd/agesa/family14/root_complex/chip.h
new file mode 100644
index 0000000000..234f931aef
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/root_complex/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_family14_root_complex_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_family14_root_complex_ops;
diff --git a/src/northbridge/amd/agesa_wrapper/family14/ssdt.asl b/src/northbridge/amd/agesa/family14/ssdt.asl
index e69012bc66..e69012bc66 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/ssdt.asl
+++ b/src/northbridge/amd/agesa/family14/ssdt.asl
diff --git a/src/northbridge/amd/agesa_wrapper/Makefile.inc b/src/northbridge/amd/agesa_wrapper/Makefile.inc
deleted file mode 100644
index 3e626ed84d..0000000000
--- a/src/northbridge/amd/agesa_wrapper/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14) += family14
diff --git a/src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig b/src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig
deleted file mode 100644
index 5659b8b5a4..0000000000
--- a/src/northbridge/amd/agesa_wrapper/family14/root_complex/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
- bool
diff --git a/src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h b/src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h
deleted file mode 100644
index 71b90c617a..0000000000
--- a/src/northbridge/amd/agesa_wrapper/family14/root_complex/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-struct northbridge_amd_agesa_wrapper_family14_root_complex_config
-{
-};
-
-extern struct chip_operations northbridge_amd_agesa_wrapper_family14_root_complex_ops;
diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig
index 0ad19f27db..1b997aefd6 100644
--- a/src/southbridge/amd/Kconfig
+++ b/src/southbridge/amd/Kconfig
@@ -11,5 +11,5 @@ source src/southbridge/amd/sb600/Kconfig
source src/southbridge/amd/rs780/Kconfig
source src/southbridge/amd/sb700/Kconfig
source src/southbridge/amd/sb800/Kconfig
-source src/southbridge/amd/cimx_wrapper/Kconfig
+source src/southbridge/amd/cimx/Kconfig
source src/southbridge/amd/sr5650/Kconfig
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 75e625d6ba..0ec5d7077f 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -12,5 +12,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
-subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx_wrapper
+subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx
diff --git a/src/northbridge/amd/agesa_wrapper/Kconfig b/src/southbridge/amd/cimx/Kconfig
index 3429255df2..38fbb49bee 100644
--- a/src/northbridge/amd/agesa_wrapper/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -17,5 +17,4 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-source src/northbridge/amd/agesa_wrapper/family14/Kconfig
-
+source src/southbridge/amd/cimx/sb800/Kconfig
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
new file mode 100644
index 0000000000..e00a072d6e
--- /dev/null
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -0,0 +1,19 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h
index 6f2d5f17a6..6f2d5f17a6 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/Amd.h
+++ b/src/southbridge/amd/cimx/sb800/Amd.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h
index a86f24b6fb..a86f24b6fb 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/AmdSbLib.h
+++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 85f110df90..dc1400f04f 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -17,13 +17,13 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+config SOUTHBRIDGE_AMD_CIMX_SB800
bool
select IOAPIC
-if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
- default "southbridge/amd/cimx_wrapper/sb800/bootblock.c"
-endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+ default "southbridge/amd/cimx/sb800/bootblock.c"
+endif #SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index ca6449495d..ca6449495d 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 93e1c310e6..93e1c310e6 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h b/src/southbridge/amd/cimx/sb800/SbEarly.h
index 2dd0e6da14..2dd0e6da14 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/SbEarly.h
+++ b/src/southbridge/amd/cimx/sb800/SbEarly.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index aaec03cbea..aaec03cbea 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h b/src/southbridge/amd/cimx/sb800/cbtypes.h
index 03a0854f67..03a0854f67 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/cbtypes.h
+++ b/src/southbridge/amd/cimx/sb800/cbtypes.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 0a09e11e86..0a09e11e86 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h
index 05db9abbe7..05db9abbe7 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/cfg.h
+++ b/src/southbridge/amd/cimx/sb800/cfg.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h
index ebd7597665..3581f2e3b0 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/chip.h
+++ b/src/southbridge/amd/cimx/sb800/chip.h
@@ -17,10 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef _CIMX_WRAPPER_SB800_CHIP_H_
-#define _CIMX_WRAPPER_SB800_CHIP_H_
+#ifndef _CIMX_SB800_CHIP_H_
+#define _CIMX_SB800_CHIP_H_
-extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops;
+extern struct chip_operations southbridge_amd_cimx_sb800_ops;
/*
* configuration set in mainboard/devicetree.cb
@@ -33,10 +33,10 @@ extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops;
* 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
* 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
*/
-struct southbridge_amd_cimx_wrapper_sb800_config
+struct southbridge_amd_cimx_sb800_config
{
u32 boot_switch_sata_ide : 1;
u8 gpp_configuration;
};
-#endif /* _CIMX_WRAPPER_SB800_CHIP_H_ */
+#endif /* _CIMX_SB800_CHIP_H_ */
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c b/src/southbridge/amd/cimx/sb800/chip_name.c
index 657081e63f..9ce89d6591 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/chip_name.c
+++ b/src/southbridge/amd/cimx/sb800/chip_name.c
@@ -20,6 +20,6 @@
#include <device/device.h>
#include "chip.h"
-struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
+struct chip_operations southbridge_amd_cimx_sb800_ops = {
CHIP_NAME("AMD South Bridge SB800")
};
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 40a18ccd4c..40a18ccd4c 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 692644357a..7367a18708 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -27,7 +27,7 @@
#include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
-#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */
+#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
/*implement in mainboard.c*/
@@ -316,8 +316,8 @@ static const struct pci_driver PORTD_driver __pci_driver = {
*/
static void sb800_enable(device_t dev)
{
- struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
- (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
+ struct southbridge_amd_cimx_sb800_config *sb_chip =
+ (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
sb800_cimx_config(sb_config);
printk(BIOS_DEBUG, "sb800_enable() ");
@@ -439,7 +439,7 @@ static void sb800_enable(device_t dev)
}
-struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
+struct chip_operations southbridge_amd_cimx_sb800_ops = {
CHIP_NAME("ATI SB800")
.enable_dev = sb800_enable,
};
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index 39762a9bec..39762a9bec 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h
index 7b165f8d8e..7b165f8d8e 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/lpc.h
+++ b/src/southbridge/amd/cimx/sb800/lpc.h
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 4b13fdbd81..4b13fdbd81 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h
index 37ca5efcf5..37ca5efcf5 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/smbus.h
+++ b/src/southbridge/amd/cimx/sb800/smbus.h
diff --git a/src/southbridge/amd/cimx_wrapper/Makefile.inc b/src/southbridge/amd/cimx_wrapper/Makefile.inc
deleted file mode 100644
index 72ad0eea31..0000000000
--- a/src/southbridge/amd/cimx_wrapper/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800
diff --git a/src/vendorcode/amd/agesa/Lib/amdlib.c b/src/vendorcode/amd/agesa/Lib/amdlib.c
index 192e34d1e5..c3364d3ca9 100644
--- a/src/vendorcode/amd/agesa/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/Lib/amdlib.c
@@ -17,7 +17,7 @@
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
@@ -25,10 +25,10 @@
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -39,7 +39,7 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
* ***************************************************************************
*
*/
@@ -145,7 +145,7 @@ WriteIo32 (
{
__outdword (Address, Data);
}
-STATIC
+STATIC
UINT64 SetFsBase (
UINT64 address
)
@@ -156,10 +156,10 @@ UINT64 SetFsBase (
__writemsr (0xC0000100, address);
return hwcr;
}
-STATIC
+STATIC
VOID
RestoreHwcr (
- UINT64
+ UINT64
value
)
{
@@ -218,7 +218,7 @@ Write64Mem8 (
{
if ((Address >> 32) == 0){
*(volatile UINT8 *) (UINTN) Address = Data;
- }
+ }
else {
UINT64 hwcrSave;
hwcrSave = SetFsBase (Address);
@@ -234,7 +234,7 @@ Write64Mem16 (
{
if ((Address >> 32) == 0){
*(volatile UINT16 *) (UINTN) Address = Data;
- }
+ }
else {
UINT64 hwcrSave;
hwcrSave = SetFsBase (Address);
@@ -250,7 +250,7 @@ Write64Mem32 (
{
if ((Address >> 32) == 0){
*(volatile UINT32 *) (UINTN) Address = Data;
- }
+ }
else {
UINT64 hwcrSave;
hwcrSave = SetFsBase (Address);
@@ -330,7 +330,7 @@ LibAmdHDTBreakPoint (
)
{
__writemsr (0xC001100A, __readmsr (0xC001100A) | 1);
- __debugbreak (); // do you really need icebp? If so, go back to asm code
+ __debugbreak (); // do you really need icebp? If so, go back to asm code
}
UINT8
LibAmdBitScanForward (
@@ -387,7 +387,7 @@ ReadTSC (
{
return __rdtsc ();
}
-VOID
+VOID
LibAmdSimNowEnterDebugger (
VOID
)
@@ -416,7 +416,7 @@ VOID F10RevDProbeFilterCritical (
_mm_mfence ();
__outdword (0xCFC, PciRegister | 2);
_mm_mfence ();
- __writemsr (0xC001001F, msrsave);
+ __writemsr (0xC001001F, msrsave);
}
VOID
@@ -447,7 +447,7 @@ IdsOutPort (
{
__outdword ((UINT16) Addr, Value);
}
-VOID
+VOID
StopHere (
VOID
)
@@ -765,7 +765,7 @@ LibAmdPciRead (
LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
} else {
LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader);
- RMWrite = RMWritePrevious | 0x0000400000000000;
+ RMWrite = RMWritePrevious | 0x0000400000000000ull;
LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
@@ -814,7 +814,7 @@ LibAmdPciWrite (
LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
} else {
LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader);
- RMWrite = RMWritePrevious | 0x0000400000000000;
+ RMWrite = RMWritePrevious | 0x0000400000000000ull;
LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
@@ -918,7 +918,7 @@ GetPciMmioAddress (
MmioIsEnabled = FALSE;
LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
if ((MsrReg & BIT0) != 0) {
- *MmioAddress = MsrReg & 0xFFFFFFFFFFF00000;
+ *MmioAddress = MsrReg & 0xFFFFFFFFFFF00000ull;
EncodedSize = (UINT32) ((MsrReg & 0x3C) >> 2);
*MmioSize = ((1 << EncodedSize) * 0x100000);
MmioIsEnabled = TRUE;
@@ -1320,7 +1320,7 @@ LibAmdAccessWidth (
return Width;
}
-VOID
+VOID
CpuidRead (
IN UINT32 CpuidFcnAddress,
OUT CPUID_DATA *Value
@@ -1329,12 +1329,12 @@ CpuidRead (
__cpuid ((int *)Value, CpuidFcnAddress);
}
-UINT8
+UINT8
ReadNumberOfCpuCores(
VOID
)
{
CPUID_DATA Value;
CpuidRead (0x80000008, &Value);
- return Value.ECX_Reg & 0xff;
+ return Value.ECX_Reg & 0xff;
}
diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc
index c9bfea9c75..7badca5d0e 100644
--- a/src/vendorcode/amd/cimx/sb800/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc
@@ -21,7 +21,7 @@
CIMX_ROOT = $(src)/vendorcode/amd/cimx
CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
-CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800
+CIMX_INC += -I$(src)/southbridge/amd/cimx/sb800
CIMX_INC += -I$(CIMX_ROOT)/sb800
romstage-y += ACPILIB.c