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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-08-25 15:29:45 -0600
committerMartin Roth <martinroth@google.com>2017-09-13 18:56:27 +0000
commit0801b335dd11f7827b6c0164f06d75e7a94fff1e (patch)
tree9ae7df47090af46ae1d84615294b85a12ced74e4
parent7e464dcb85354e22e733d94ef2b3e2c77fca22dc (diff)
downloadcoreboot-0801b335dd11f7827b6c0164f06d75e7a94fff1e.tar.xz
amd/stoneyridge: Make cbmem_top SMM aware
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to HAVE_SMI_HANDLER. Change the value returned by cbmem_top() to carve out a range to be used by TSEG. The SMM Mask register has a granularity of 128KB but align the value to 16MB to keep down the number of variable MTRRs required. Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/amd/stoneyridge/Kconfig2
-rw-r--r--src/soc/amd/stoneyridge/ramtop.c4
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 08613fe08a..f8768e7ea7 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -289,7 +289,7 @@ config STONEYRIDGE_UART
config SMM_TSEG_SIZE
hex
- default 0x800000 if HAVE_SMI_HANDLER
+ default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
default 0x0
config ACPI_CPU_STRING
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index c81e73b4e1..bdad8d6057 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -41,5 +41,7 @@ void *cbmem_top(void)
if (!tom.lo)
return 0;
else
- return (void *)restore_top_of_low_cacheable();
+ /* 16MB alignment to keep MTRR usage low */
+ return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
+ - CONFIG_SMM_TSEG_SIZE, 16*MiB);
}