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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-05-04 13:36:23 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-06 08:47:28 +0000 |
| commit | 0985fba3705607ecf571082b241018c0d1bd962d (patch) | |
| tree | db857b4c186f904536e6d5c388f370a73e0fdfa9 | |
| parent | 4a36cfb625653a1849edd7651ed81a0c7007a612 (diff) | |
| download | coreboot-0985fba3705607ecf571082b241018c0d1bd962d.tar.xz | |
mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree
BUG=None
TEST=Build and boot the mainboard.
Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cfe221f994..c891e6e376 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -289,11 +289,11 @@ chip soc/intel/jasperlake device pnp 0c09.0 on end end end # eSPI Interface - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI + device pci 1f.5 on end # PCH SPI device pci 1f.7 off end # Intel Trace Hub end end |