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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2011-08-01 14:24:02 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-08-04 17:28:36 +0200 |
| commit | 0df0e14fb5b613e76ff022359c55d5df5633b40f (patch) | |
| tree | d2ba6734d1ee6220a7d7b55d66c109fbc79a8718 | |
| parent | e089a3f68ddbbaaceb25d00322b3e7ccc27a48a8 (diff) | |
| download | coreboot-0df0e14fb5b613e76ff022359c55d5df5633b40f.tar.xz | |
Add voltage control of southbridge and RAM on ms7135
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/126
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/msi/ms7135/cmos.layout | 16 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7135/romstage.c | 28 |
2 files changed, 41 insertions, 3 deletions
diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout index 53fdef5b0a..694554dd8d 100644 --- a/src/mainboard/msi/ms7135/cmos.layout +++ b/src/mainboard/msi/ms7135/cmos.layout @@ -43,6 +43,8 @@ entries 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu +448 4 e 10 ram_voltage +452 4 e 11 nf4_voltage 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -74,10 +76,10 @@ enumerations 7 0 Network 7 1 HDD 7 2 Floppy +#7 3 ROM 7 8 Fallback_Network 7 9 Fallback_HDD 7 10 Fallback_Floppy -#7 3 ROM 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz @@ -91,8 +93,16 @@ enumerations 9 6 25.0% 9 7 12.5% -checksums +10 0 2.55 +10 1 2.50 +10 2 2.60 +10 3 2.65 +10 4 2.70 -checksum 392 983 984 +11 0 1.50 +11 1 1.55 +11 2 1.60 +checksums +checksum 392 983 984 diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 80b3c19bde..773d93e8dc 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -48,6 +48,10 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif + #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -66,6 +70,27 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" +static void ms7135_set_ram_voltage(void) +{ + u8 b; + b = read_option(ram_voltage, 0); + if (b > 4) /* default if above 2.70v */ + b = 0; + printk(BIOS_INFO, "setting RAM voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x00, b); +} + +static void ms7135_set_nf4_voltage(void) +{ + u8 b; + b = read_option(nf4_voltage, 0); + if (b > 2) /* default if above 1.60v */ + b = 0; + b |= 0x10; + printk(BIOS_INFO, "setting NF4 voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x02, b); +} + static void sio_setup(void) { u32 dword; @@ -136,6 +161,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); + ms7135_set_nf4_voltage(); + ms7135_set_ram_voltage(); + #if CONFIG_DEBUG_SMBUS dump_spd_registers(&ctrl[0]); dump_smbus_registers(); |