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| author | Furquan Shaikh <furquan@google.com> | 2019-04-22 23:45:06 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-04-24 16:23:38 +0000 |
| commit | 131134288be3d8851e7e4e7268fac8b9072ef83c (patch) | |
| tree | 0c1c84d082a08562576f1a1aada890f9cfc5732f | |
| parent | 77fb3632a4a3d3004b3aa4950967be9164d9711d (diff) | |
| download | coreboot-131134288be3d8851e7e4e7268fac8b9072ef83c.tar.xz | |
mb/google/hatch/var/kohaku: Skip UART0 config in FSP
Similar to hatch(CB:32278), this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in
FSP.
This change also adds a device to kohaku override tree to ensure that
the settings in it take effect.
BUG=b:130310626
Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 6e6414e8a8..d564918a57 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -10,9 +10,12 @@ chip soc/intel/cannonlake [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + device domain 0 on + end + end |