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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-30 16:02:17 -0600 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-01 21:58:34 +0000 |
| commit | 14ef26b07b2f2d0150005e85de45af672e2b492d (patch) | |
| tree | 37f528915ebe1b6198bc94170e8fa5fb46e7d2be | |
| parent | 7a694318e5f549a3860fde0600c93e853e4788d6 (diff) | |
| download | coreboot-14ef26b07b2f2d0150005e85de45af672e2b492d.tar.xz | |
amd/stoneyridge: Consolidate duplicate comment
Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 78a4038a16..8630ea92a7 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -30,14 +30,10 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* Offsets from ACPI_MMIO_BASE */ +/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */ + #define APU_SMI_BASE 0xfed80200 -/* - * Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ #define PM_MMIO_BASE 0xfed80300 #define APU_UART0_BASE 0xfedc6000 |