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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-26 16:23:41 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 14:32:34 +0000 |
| commit | 1d9a46ba9a289691325d2dece09c3d4ebd15439a (patch) | |
| tree | 170a53ff5401e2e82528f79b19d95f459d5716e1 | |
| parent | d61e347bffae29e6db179641652602226711e401 (diff) | |
| download | coreboot-1d9a46ba9a289691325d2dece09c3d4ebd15439a.tar.xz | |
amd/stoneyridge: Load AOAC and USB gnvs values
Indicate the devices that are enabled. This is somewhat rudimentary, but
could be improved in a later patch (e.g. get settings from devicetree).
Calculate values that may be used for reinitializing the xHCI firmware.
Add the EHCI BAR's current base address to gnvs.
BUG=b:77602074
Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28767
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 46 |
2 files changed, 51 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index c54a7d43cc..a3c4c7ca8d 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -429,6 +429,11 @@ struct soc_power_reg { uint16_t wake_from; }; +#define XHCI_FW_SIG_OFFSET 0xc +#define XHCI_FW_ADDR_OFFSET 0x6 +#define XHCI_FW_SIZE_OFFSET 0x8 +#define XHCI_FW_BOOTRAM_SIZE 0x8000 + void enable_aoac_devices(void); void sb_enable_rom(void); void configure_stoneyridge_i2c(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 8984c40c1f..b122f8311c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -886,6 +886,50 @@ void southbridge_init(void *chip_info) sb_clear_pm1_status(); } +static void set_sb_final_nvs(void) +{ + uintptr_t amdfw_rom; + uintptr_t xhci_fw; + uintptr_t fwaddr; + size_t fwsize; + const struct device *sd, *sata, *ehci; + + struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs == NULL) + return; + + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + /* Rely on these being in sync with devicetree */ + sd = dev_find_slot(0, SD_DEVFN); + gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0; + sata = dev_find_slot(0, SATA_DEVFN); + gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.espi = 1; + + amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + + fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + gnvs->fw00 = 0; + gnvs->fw01 = ((32 * KiB) << 16) + 0; + gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; + gnvs->fw03 = fwsize << 16; + + ehci = dev_find_slot(0, EHCI1_DEVFN); + gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) + & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + void southbridge_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; @@ -893,6 +937,8 @@ void southbridge_final(void *chip_info) if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); + + set_sb_final_nvs(); } /* |