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| author | Yidi Lin <yidi.lin@mediatek.com> | 2016-04-06 16:28:06 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-09 08:35:39 +0200 |
| commit | 1efc72affa03d25c728e0ecefb08239e725ffae9 (patch) | |
| tree | 0fc1f9f7fef69e60e70ac1e5f93053d7c321895c | |
| parent | 374c50e8764b5cc7b35699a13abefdf8c6c4acf0 (diff) | |
| download | coreboot-1efc72affa03d25c728e0ecefb08239e725ffae9.tar.xz | |
google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1
SPI level shifter is controlled by SRCLKENA0 after elm-rev1.
We don't need to configure it in the bootloader.
BUG=chrome-os-partner:51725
TEST=emerge-elm coreboot
Change-Id: I01ec00965b87ae370b72d3c0521fb37268714cf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3234065e33c46bc2d67a96939422d318919d5e7a
Original-Change-Id: Iafed0cd7562eb5921af6b17f73a067d469143e02
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/337421
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/google/oak/bootblock.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 325889cbb3..04a3a550ec 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -81,7 +81,8 @@ void bootblock_mainboard_init(void) nor_set_gpio_pinmux(); /* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */ - if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) + if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 && + board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8) gpio_output(PAD_SRCLKENAI2, 1); /* Init i2c bus 2 Timing register for TPM */ |