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authorMatt DeVillier <matt.devillier@gmail.com>2019-10-10 13:24:12 -0500
committerPatrick Georgi <pgeorgi@google.com>2019-10-22 13:00:12 +0000
commit231c74cacff24e0d96c879b5c36ca4ab76ee35aa (patch)
tree6ebf20a38345a5670dcc0d4e748306662cc9713c
parent046382b8c541655af31559aaf060ff3cf987a245 (diff)
downloadcoreboot-231c74cacff24e0d96c879b5c36ca4ab76ee35aa.tar.xz
google/chell: Update ICC_MAX configuration
Correct ICC_MAX values per SKL-Y EDS spec. Adapted from chromium commit 1c4e89e8 [Chell: Update ICC_MAX configuration] Original-Change-Id: Ic660cc6a2d11e995a86a30ddde800d096d93e012 Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/593715 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ia31ce432cf979d574d84e9205a287f87de5de057 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
-rw-r--r--src/mainboard/google/glados/variants/chell/devicetree.cb10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb
index 5b82e5aaad..89f1c08b75 100644
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -81,7 +81,7 @@ chip soc/intel/skylake
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 35A | 35A |
+ #| IccMax | 4A | 24A | 24A | 24A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
@@ -93,7 +93,7 @@ chip soc/intel/skylake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(7),
+ .icc_max = VR_CFG_AMP(4),
.voltage_limit = 1520,
}"
@@ -106,7 +106,7 @@ chip soc/intel/skylake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(34),
+ .icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
}"
@@ -119,7 +119,7 @@ chip soc/intel/skylake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(35),
+ .icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
}"
@@ -132,7 +132,7 @@ chip soc/intel/skylake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(35),
+ .icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
}"