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authorRaul E Rangel <rrangel@chromium.org>2019-04-23 16:02:15 -0600
committerMartin Roth <martinroth@google.com>2019-05-15 16:01:48 +0000
commit29150c83df8630a817e81eef593dd93fdb37b09f (patch)
tree7b096a18165fc0723470c1e069cbe9b5e3436a7a
parentcd51d7ced5a4996253c6dfc816ab7ef82533b2da (diff)
downloadcoreboot-29150c83df8630a817e81eef593dd93fdb37b09f.tar.xz
soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller
We need to support entering D3Cold from the OS to work around a bug in the SDHC where the data lines get stuck always reading zeros. BUG=b:122749418 TEST=Verified the linux kernel can transition between D3 and D0. Also verified that the device can suspend and resume and continue to have a functioning SD controller after. Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl31
1 files changed, 28 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 15e4d2f122..1334df11c4 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -56,6 +56,16 @@ Device(SBUS) {
/* 0:14.7 - SD Controller */
Device(SDCN) {
Name(_ADR, 0x00140007)
+
+ Method(_PS0) {
+ FDDC(24, 0)
+ }
+ Method(_PS3) {
+ FDDC(24, 3)
+ }
+ Method(_PSC) {
+ Return(SDTD)
+ }
} /* end SDCN */
Name(CRES, ResourceTemplate() {
@@ -286,8 +296,9 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
offset (0x1e70), /* SD D3 Control */
SDTD, 2,
, 1,
+ SDPD, 1,
+ , 1,
, 1,
- , 2,
SDRT, 1,
SDSC, 1,
@@ -433,7 +444,14 @@ Method(FDDC, 2, Serialized)
/* todo Case(15) { STD0()} */ /* SATA */
Case(18) { U2D0()} /* EHCI */
Case(23) { U3D0()} /* XHCI */
-/* todo Case(24) { SDD0()} */ /* SD */
+ Case(24) { /* SD */
+ Store(0x00, SDTD)
+ Store(One, SDPD)
+ Store(SDDS, Local0)
+ while(LNotEqual(Local0,0x7)) {
+ Store(SDDS, Local0)
+ }
+ }
}
} else {
/* put device into D3cold */
@@ -489,7 +507,14 @@ Method(FDDC, 2, Serialized)
/* todo Case(15) { STD3()} */ /* SATA */
Case(18) { U2D3()} /* EHCI */
Case(23) { U3D3()} /* XHCI */
-/* todo Case(24) { SDD3()} */ /* SD */
+ Case(24) { /* SD */
+ Store(Zero, SDPD)
+ Store(SDDS, Local0)
+ while(LNotEqual(Local0,0x0)) {
+ Store(SDDS, Local0)
+ }
+ Store(0x03, SDTD)
+ }
}
/* Turn off Power */
if(LEqual(I0TD, 3)) {