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authorVaibhav Shankar <vaibhav.shankar@intel.com>2018-03-19 18:56:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-03-23 08:56:19 +0000
commit2da6ec40bbbf9b30afd4372587235d14a455f88f (patch)
treea6b0d1879ba33b6bb9c07c5750bfd4df338a8638
parent83308660677056ccaea1a70494dac7874be43f41 (diff)
downloadcoreboot-2da6ec40bbbf9b30afd4372587235d14a455f88f.tar.xz
soc/intel/cannonlake: Enable low power S0 Idle capability
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0 if S0ix is enabled for the platform. This also sets the FSPUPD to indicate the status of S0ix on the platform. TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table - FADT.Flags[21] bit. Change-Id: I6214ebb61f25ef8b704e60c8474808493c92e6f6 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25292 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/acpi.c3
-rw-r--r--src/soc/intel/cannonlake/chip.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 9dcaa338c9..0134b86865 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -187,6 +187,9 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ if(config->s0ix_enable)
+ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}
uint32_t soc_read_sci_irq_select(void)
{
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index ca2f9a35ec..b2689b0608 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -228,6 +228,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
+ /* S0ix */
+ params->PchPmSlpS0Enable = config->s0ix_enable;
+
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =