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| author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2021-03-16 18:05:13 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-22 11:25:26 +0000 |
| commit | 31f383686a5aea58092330b29a9a7f128c2e3889 (patch) | |
| tree | 3364546bd3c0b970d23623c4a91848969eed4ca6 | |
| parent | 9f5261e5fab2059b1b5f173388b0f0c1b7f5f308 (diff) | |
| download | coreboot-31f383686a5aea58092330b29a9a7f128c2e3889.tar.xz | |
mb/google/brya: Enable S0ix
This change enables S0ix for brya platform.
BUG=b:181843816
TEST=Built image and booted to kernel.
Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 33be8623f7..3155d04f82 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # S0ix enable + register "s0ix_enable" = "1" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 |