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authorWonkyu Kim <wonkyu.kim@intel.com>2020-03-02 22:18:26 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-07 20:44:21 +0000
commit34944be317657e29a4bcba82f7f52f12ed90a327 (patch)
treebf250e99b60a99875c60c4edc5038a17d78ad041
parentdd3604422f5ca4672dc2919805a09c74e732066c (diff)
downloadcoreboot-34944be317657e29a4bcba82f7f52f12ed90a327.tar.xz
mb/intel/tglrvp: Update display ports for RVP
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229 Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb1
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c10
2 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index e61690ea41..5888db0474 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -52,6 +52,7 @@ chip soc/intel/tigerlake
# enabling EDP in PortA
register "DdiPortAConfig" = "1"
+ register "DdiPortBHpd" = "1"
register "DdiPort1Hpd" = "1"
register "DdiPort1Ddc" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index 46ed5a20a9..073926ace5 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -61,7 +61,6 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
-
/*Audio */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */
@@ -83,6 +82,15 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
+ /* DP */
+ PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */
+ PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */
+ PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */
+ PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */
+ PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */
+ PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */
+ PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */
+ PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */
};
const struct pad_config *variant_gpio_table(size_t *num)