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authorMartin Roth <gaumless@gmail.com>2014-05-21 15:07:26 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-22 05:22:25 +0200
commit351aff85ee0c694e791ac7647ed9f49d7d9e6e99 (patch)
treecd8b8c1480ba884e573cc0719dc2a7428e1d27b3
parentefac717f3cf6daad582875657a1ef7db72ab59c8 (diff)
downloadcoreboot-351aff85ee0c694e791ac7647ed9f49d7d9e6e99.tar.xz
device/pci_ids.h: defines for new Intel LPC devices
Add defines for the Cave Creek and Rangeley LPC devices. These chipsets will be added shortly. This file is outside of any of the directories that will be touched by those additions, so it's getting changed in its own commit. Change-Id: Ia829282b2ad67eef09689858500bc7f93a1cd05b Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5810 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/include/device/pci_ids.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 50ab96caca..4f15c377be 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2531,10 +2531,13 @@
#define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914
#define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912
+#define PCI_DEVICE_ID_INTEL_CAVECREEK_LPC 0x2310
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
+#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN 0x1f38
+#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX 0x1f3b
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
/* Intel 82801E (C-ICH) */