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| author | Varadarajan Narayanan <varada@codeaurora.org> | 2016-01-06 14:14:59 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-10 22:57:50 +0200 |
| commit | 35d4a35669c57e1c121b5aa6cbd0004b2e0d497b (patch) | |
| tree | 1744df7f9c904469b7fe70184dd050001ebe9cf9 | |
| parent | 3a749ee654f5e6035d207148167c287374d1bd00 (diff) | |
| download | coreboot-35d4a35669c57e1c121b5aa6cbd0004b2e0d497b.tar.xz | |
soc/qualcomm/ipq40xx: Streamline memory map
BUG=chrome-os-partner:49249
TEST=Able to compile and boot to depthcharge
BRANCH=none
Change-Id: I042fce58526b1c2add6b930429bf397e0dcfad2c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 66a630db6132e0e8a736b635d65e9e11c269b54a
Original-Change-Id: Ie2b6f59b3dbbac8117636c103d4d0acb782f4cb3
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333322
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index de8488ac53..5e9707754d 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -36,8 +36,8 @@ SECTIONS PRERAM_CBFS_CACHE(0x0A0C0000, 93K) - TTB_SUBTABLES(0x0A0E0000, 4K) TTB(0x0A0F0000, 16K) + TTB_SUBTABLES(0x0A0F4000, 4K) REGION_END(wifi_imem_0, 0x0A100000) /* ==^^^== WIFI_IMEM_0_END 0x0A100000 ==^^^== */ @@ -57,8 +57,8 @@ SECTIONS /* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */ DRAM_START(0x80000000) - RAMSTAGE(0x80640000, 128K) - SYMBOL(memlayout_cbmem_top, 0x89F80000) - POSTRAM_CBFS_CACHE(0x89F80000, 384K) - DMA_COHERENT(0x8A000000, 2M) + SYMBOL(memlayout_cbmem_top, 0x87280000) + POSTRAM_CBFS_CACHE(0x87280000, 384K) + RAMSTAGE(0x872e0000, 128K) + DMA_COHERENT(0x87300000, 2M) } |