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authorNickey Yang <nickey.yang@rock-chips.com>2017-05-16 10:40:49 +0800
committerJulius Werner <jwerner@chromium.org>2017-05-18 01:00:37 +0200
commit36b09b8a6c3367dded5c3f0c6a1dc1d16d9a1335 (patch)
tree3b7d0b21d73782cc48d3623b8c9827430dc2f028
parentfe122d4dfc130be1e87b367b0dc9b39044b262bd (diff)
downloadcoreboot-36b09b8a6c3367dded5c3f0c6a1dc1d16d9a1335.tar.xz
google/scarlet: Enable innolux,p079zca MIPI panel
TEST=Boot from scarlet, and mipi panel works Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748 Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/mainboard/google/gru/devicetree.scarlet.cb14
1 files changed, 13 insertions, 1 deletions
diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb
index 2c316545f0..f1129a4980 100644
--- a/src/mainboard/google/gru/devicetree.scarlet.cb
+++ b/src/mainboard/google/gru/devicetree.scarlet.cb
@@ -15,6 +15,18 @@
chip soc/rockchip/rk3399
device cpu_cluster 0 on end
- register "vop_mode" = "VOP_MODE_NONE"
+ register "vop_mode" = "VOP_MODE_MIPI"
register "framebuffer_bits_per_pixel" = "32"
+ register "panel_pixel_clock" = "56900"
+ register "panel_refresh" = "60"
+ register "panel_ha" = "768"
+ register "panel_hbl" = "120"
+ register "panel_hso" = "40"
+ register "panel_hspw" = "40"
+ register "panel_va" = "1024"
+ register "panel_vbl" = "44"
+ register "panel_vso" = "20"
+ register "panel_vspw" = "4"
+ register "panel_display_on_mdelay" = "120"
+ register "panel_video_mode_mdelay" = "5"
end