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authorLee Leahy <leroy.p.leahy@intel.com>2015-09-17 12:35:10 -0700
committerAaron Durbin <adurbin@gmail.com>2015-10-11 23:55:34 +0000
commit3c4053fa59a8654b2f10cf175915914c37da9daf (patch)
tree660bb7b5670d355cf556e0ac3780ec9a6fe5a42c
parent13cd3310a55c5683fb0b1176444ad8f5e5243945 (diff)
downloadcoreboot-3c4053fa59a8654b2f10cf175915914c37da9daf.tar.xz
intel SOC common: Remove unused parameters
Eliminate unused parameters from the console initialization. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/301204 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11814 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/mainboard/google/cyan/com_init.c2
-rwxr-xr-xsrc/mainboard/intel/strago/com_init.c2
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c2
-rw-r--r--src/soc/intel/common/romstage.c10
-rw-r--r--src/soc/intel/common/romstage.h4
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c2
6 files changed, 10 insertions, 12 deletions
diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c
index bce0666fba..00f79dcb87 100644
--- a/src/mainboard/google/cyan/com_init.c
+++ b/src/mainboard/google/cyan/com_init.c
@@ -24,7 +24,7 @@
#include <soc/pci_devs.h>
#include <soc/romstage.h>
-void mainboard_pre_console_init(struct romstage_params *params)
+void mainboard_pre_console_init(void)
{
uint32_t reg;
uint32_t *pad_config_reg;
diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c
index a15d8c38df..d29eed3aab 100755
--- a/src/mainboard/intel/strago/com_init.c
+++ b/src/mainboard/intel/strago/com_init.c
@@ -33,7 +33,7 @@
/* family number in high byte and inner pad number in lowest byte */
-void mainboard_pre_console_init(struct romstage_params *params)
+void mainboard_pre_console_init(void)
{
uint32_t reg;
uint32_t *pad_config_reg;
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2286cd48e7..00710fe837 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -170,7 +170,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
}
/* SOC initialization before the console is enabled */
-void soc_pre_console_init(struct romstage_params *params)
+void soc_pre_console_init(void)
{
/* Early chipset initialization */
program_base_addresses();
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index f4ee250203..e1095b2f09 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -70,8 +70,8 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
memset(&pei_data, 0, sizeof(pei_data));
/* Call into pre-console init code. */
- soc_pre_console_init(&params);
- mainboard_pre_console_init(&params);
+ soc_pre_console_init();
+ mainboard_pre_console_init();
/* Start console drivers */
console_init();
@@ -245,8 +245,7 @@ __attribute__((weak)) void mainboard_check_ec_image(
}
/* Board initialization before the console is enabled */
-__attribute__((weak)) void mainboard_pre_console_init(
- struct romstage_params *params)
+__attribute__((weak)) void mainboard_pre_console_init(void)
{
}
@@ -469,9 +468,8 @@ __attribute__((weak)) void soc_after_temp_ram_exit(void)
}
/* SOC initialization before the console is enabled */
-__attribute__((weak)) void soc_pre_console_init(struct romstage_params *params)
+__attribute__((weak)) void soc_pre_console_init(void)
{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* SOC initialization before RAM is enabled */
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 56ab467085..c0c7a7b70d 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -80,7 +80,7 @@ struct romstage_params {
void mainboard_check_ec_image(struct romstage_params *params);
void mainboard_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *memory_params);
-void mainboard_pre_console_init(struct romstage_params *params);
+void mainboard_pre_console_init(void);
void mainboard_romstage_entry(struct romstage_params *params);
void mainboard_save_dimm_info(struct romstage_params *params);
void mainboard_add_dimm_info(struct romstage_params *params,
@@ -100,7 +100,7 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
MEMORY_INIT_UPD *new);
void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd);
-void soc_pre_console_init(struct romstage_params *params);
+void soc_pre_console_init(void);
void soc_pre_ram_init(struct romstage_params *params);
void soc_romstage_init(struct romstage_params *params);
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 6804459c19..0343491f3f 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -47,7 +47,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
/* SOC initialization before the console is enabled */
-void soc_pre_console_init(struct romstage_params *params)
+void soc_pre_console_init(void)
{
/* System Agent Early Initialization */
systemagent_early_init();