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authorJustin TerAvest <teravest@chromium.org>2018-03-16 12:50:13 -0600
committerAaron Durbin <adurbin@chromium.org>2018-03-19 15:31:48 +0000
commit3cb00ef84e553ced68f60c0a1f6cf74e24188602 (patch)
treef346cf597db75be4006fb670cfcfdd43c25b14af
parent22595f6e45a5f97bdeb182ef809a5c9a1815052d (diff)
downloadcoreboot-3cb00ef84e553ced68f60c0a1f6cf74e24188602.tar.xz
mb/google/octopus: Configure PERST_0 pin
According to the schematic, Octopus boards have WLAN_PE_RST connected to GPIO_164. This change configures that properly in devicetree. BUG=None TEST=None Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25248 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/octopus/variants/baseboard/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index e7ee9d3a55..1174d2c721 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -3,6 +3,9 @@ chip soc/intel/apollolake
device lapic 0 on end
end
+ # GPIO for PERST_0 (WLAN_PE_RST)
+ register "prt0_gpio" = "GPIO_164"
+
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-16.33.
# [14:8] steps of delay for HS400, each 125ps.