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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-01 06:32:20 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-02 22:00:01 +0000 |
| commit | 3e893bbed55f678155dfb58750376ad60a85e119 (patch) | |
| tree | 4fdd562fe26820b8a75783ddc5479f866312cdf7 | |
| parent | 6a8ce0d250f4dbaa2f253e566cf76e20f753d131 (diff) | |
| download | coreboot-3e893bbed55f678155dfb58750376ad60a85e119.tar.xz | |
intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGE
Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/cpu/intel/socket_mPGA604/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/e7505/memmap.c | 14 |
4 files changed, 10 insertions, 11 deletions
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 717c5c2b6a..746fa353df 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -9,10 +9,6 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -else cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index d80ddf3efb..29613a92f4 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select RELOCATABLE_RAMSTAGE + select POSTCAR_STAGE config HW_SCRUBBER bool diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 57c870fde4..7f7c5e40aa 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -6,4 +6,6 @@ ramstage-y += memmap.c romstage-y += raminit.c romstage-y += debug.c romstage-y += memmap.c + +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 4a80608e81..48527fdd96 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -37,9 +37,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -59,8 +60,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } |