summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2015-09-03 16:19:42 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-10 09:48:47 +0000
commit44b01fdcd7bbd7e619f496530d3bfbea69f7fce9 (patch)
tree732aee3d78a4ac8d51e96795d5578c5580571f3b
parente067083d08b391882c7a773d0a70073d28dc17b4 (diff)
downloadcoreboot-44b01fdcd7bbd7e619f496530d3bfbea69f7fce9.tar.xz
glados: Misc code cleanups
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/google/glados/ec.c13
-rw-r--r--src/mainboard/google/glados/pei_data.c22
-rw-r--r--src/mainboard/google/glados/romstage.c1
-rw-r--r--src/mainboard/google/glados/spd/spd.c6
4 files changed, 19 insertions, 23 deletions
diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c
index c491ad5787..5473cfcf3b 100644
--- a/src/mainboard/google/glados/ec.c
+++ b/src/mainboard/google/glados/ec.c
@@ -25,11 +25,9 @@
void mainboard_ec_init(void)
{
- printk(BIOS_DEBUG, "mainboard_ec_init\n");
- post_code(0xf0);
+ printk(BIOS_DEBUG, "mainboard: EC init\n");
- /* Restore SCI event mask on resume. */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
@@ -39,10 +37,8 @@ void mainboard_ec_init(void)
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
- /*
- * Set SCI mask.OS may not generate SMI event to set
- * this on S3 resume.
- */
+
+ /* Restore SCI event mask */
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
@@ -51,5 +47,4 @@ void mainboard_ec_init(void)
/* Clear wake event mask */
google_chromeec_set_wake_mask(0);
- post_code(0xf1);
}
diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c
index 55d7f08aeb..6d2ae1547d 100644
--- a/src/mainboard/google/glados/pei_data.c
+++ b/src/mainboard/google/glados/pei_data.c
@@ -27,22 +27,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* DQ byte map */
const u8 dq_map[2][12] = {
- {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
- 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
- {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC ,
- 0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
- {0, 1, 3, 2, 4, 5, 6, 7},
- {1, 0, 4, 5, 2, 3, 6, 7} };
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
- /* Rcomp resistor*/
- const u16 RcompResistor[3] = {200, 81, 162 };
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 200, 81, 162 };
- /* Rcomp target*/
- const u16 RcompTarget[5] = {100, 40, 40, 23, 40};
-
- pei_data->ec_present = 1;
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 0639418f29..315ddb9de8 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -24,6 +24,7 @@
#include <memory_info.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c
index fc9cb53b39..0a17d68a47 100644
--- a/src/mainboard/google/glados/spd/spd.c
+++ b/src/mainboard/google/glados/spd/spd.c
@@ -22,9 +22,11 @@
#include <cbfs.h>
#include <console/console.h>
#include <gpio.h>
-#include <string.h>
+#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
+#include <string.h>
+
#include "../gpio.h"
#include "spd.h"
@@ -94,7 +96,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
};
spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
- printk(BIOS_ERR, "SPD index %d\n", spd_index);
+ printk(BIOS_INFO, "SPD index %d\n", spd_index);
/* Load SPD data from CBFS */
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,