summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKayalvizhi Dhandapani <kayalvizhid@ami.com>2014-10-07 14:34:01 -0400
committerMarc Jones <marc.jones@se-eng.com>2014-10-09 21:59:45 +0200
commit454625c5cf4adecb5b80777503bc600c8b139004 (patch)
tree753330c0244e6419ab51e8e6c374293e471203d5
parent2c0f46afbbee078881ad9e9a99f5c219c2ed528e (diff)
downloadcoreboot-454625c5cf4adecb5b80777503bc600c8b139004.tar.xz
intel/fsp_baytrail: Fix SMM/SMI
With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
-rw-r--r--src/mainboard/intel/bayleybay_fsp/devicetree.cb2
-rw-r--r--src/soc/intel/fsp_baytrail/Kconfig4
-rw-r--r--src/soc/intel/fsp_baytrail/cpu.c10
3 files changed, 13 insertions, 3 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index befd3dce25..356c8df5f3 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail
register "SataMode" = "SATA_MODE_AHCI"
register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT"
+ register "MrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index cb4757bca3..e9391c302b 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -31,12 +31,16 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select DYNAMIC_CBMEM
+ select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
select PARALLEL_MP
select REG_SCRIPT
+ select SMM_MODULES
+ select SMM_TSEG
+ select BAYTRAIL_SMM
select SMP
select SPI_FLASH
select SSE2
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index f260880d39..6f1e9c4acd 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -148,14 +148,20 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params)
runtime->apic_id_to_cpu[i] = mp_get_apic_id(i);
}
-static void asmlinkage
-cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime)
+static void asmlinkage cpu_smm_do_relocation(void *arg)
{
#ifndef CONFIG_MAX_CPUS
#error CONFIG_MAX_CPUS must be set.
#endif
msr_t smrr;
em64t100_smm_state_save_area_t *smm_state;
+ const struct smm_module_params *p;
+ const struct smm_runtime *runtime;
+ int cpu;
+
+ p = arg;
+ runtime = p->runtime;
+ cpu = p->cpu;
if (cpu >= CONFIG_MAX_CPUS) {
printk(BIOS_CRIT,