summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDave Frodin <dave.frodin@se-eng.com>2015-02-06 07:25:11 -0700
committerDave Frodin <dave.frodin@se-eng.com>2015-02-14 00:31:06 +0100
commit4675c598a4f966e5159c29eb502c7bb3917ccbf9 (patch)
treedfa16028977446b09be23b23e5d58fcf45f1b265
parentf5b65a34fdebc251d581eb6f9bc24e0f32b14f29 (diff)
downloadcoreboot-4675c598a4f966e5159c29eb502c7bb3917ccbf9.tar.xz
southbridge/amd/pi: Combine and correct the IRQ text strings
This combines the Avalon and Bolton tables of text descriptions of the IRQ assignments. It also corrects the text string for the SD controller on Bolton. Test: This was verified on amd/lamar. Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8374 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
-rw-r--r--src/southbridge/amd/pi/hudson/amd_pci_int_types.h20
1 files changed, 7 insertions, 13 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index 517c8926c0..35a4e89206 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
@@ -20,26 +20,20 @@
#ifndef AMD_PCI_INT_TYPES_H
#define AMD_PCI_INT_TYPES_H
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
const char * intr_types[] = {
[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
- [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t",
+ [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",
[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
- [0x40] = "IDE\t", "SATA\t",
- [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
-};
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
-const char * intr_types[] = {
- [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
- [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
- [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t",
- [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
- [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB",
+ [0x7F] = "RSVD\t",
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON)
[0x40] = "RSVD\t", "SATA\t",
[0x60] = "RSVD\t", "RSVD\t", "GPIO\t",
-};
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+ [0x40] = "IDE\t", "SATA\t",
+ [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
#endif
+};
#endif /* AMD_PCI_INT_TYPES_H */