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authorChristoph Pomaska <cp_public@gmx.de>2018-01-01 01:48:21 +0100
committerNico Huber <nico.h@gmx.de>2018-01-10 22:04:33 +0000
commit48ac29ee4cbd159932d919a3d791cfe42d950b28 (patch)
tree304b8699a746ab60a38db9f7ef48cd339d4c39ef
parentbb9bdeb59480cade6f428237c6727d805d6c5f4c (diff)
downloadcoreboot-48ac29ee4cbd159932d919a3d791cfe42d950b28.tar.xz
util/inteltool: Add Skylake Desktop Northbridge
Add the 8086:191f North/Host Bridge to the list of definitions. Adding the definiton makes the Northbridge get recognized by inteltool. It is found in the Intel i5-6600K CPU: https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz Change-Id: Id746d1e8b3bb90b3b68a2f6c372890671dd61b5f Signed-off-by: Christoph Pomaska <cp_public@gmx.de> Reviewed-on: https://review.coreboot.org/23055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--util/inteltool/inteltool.c2
-rw-r--r--util/inteltool/inteltool.h3
-rw-r--r--util/inteltool/memory.c1
-rw-r--r--util/inteltool/pcie.c3
4 files changed, 8 insertions, 1 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 32801df02e..688e74342f 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -115,6 +115,8 @@ static const struct {
"6th generation (Skylake-H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST,
"6th generation (Skylake-S/H family) Core Processor (Workstation)" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D,
+ "6th generation (Skylake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 37a13373b9..512bdbaee3 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -223,7 +223,8 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
-#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918
+#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */
+#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */
/* Intel GPUs */
#define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 87cd5d8f06..67a29a7e02 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -219,6 +219,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
+ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 78d69feda3..2eb65c1819 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -265,6 +265,7 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
+ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
@@ -385,6 +386,7 @@ int print_dmibar(struct pci_dev *nb)
break;
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
+ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
dmi_registers = skylake_dmi_registers;
size = ARRAY_SIZE(skylake_dmi_registers);
dmibar_phys = pci_read_long(nb, 0x68);
@@ -489,6 +491,7 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
+ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;