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authorHarry Pan <harry.pan@intel.com>2017-02-02 15:42:25 +0800
committerAaron Durbin <adurbin@chromium.org>2017-02-03 15:36:27 +0100
commit4a282b84192d4b8ba62521c0dc87db1872853ab0 (patch)
tree2e0f61e4e1bc4332cddf789164b8be5011118c90
parent84e6881ba5bdba7dc54c82b8f372079191ba4cd8 (diff)
downloadcoreboot-4a282b84192d4b8ba62521c0dc87db1872853ab0.tar.xz
mainboard/google/snappy: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:62110 BRANCH=reef TEST=Apply new firmware to evaluate Octane benchmark score. Change-Id: I51734051586753677129314b5273fb275c74f5d2 Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://review.coreboot.org/18283 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 6d7c8cacfc..c83306d3d1 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -53,6 +53,8 @@ chip soc/intel/apollolake
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
+ # Set RAPL PL2 to 15W.
+ register "tdp_pl2_override_mw" = "15000"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"