mb/purism/librem_cnl: Add new board/variant Librem 14

Add support for the CometLake-U based Librem 14 laptop.

Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 1047 insertions, 1 deletions

diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index 919240244f..eeb4d3b9db 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -21,15 +21,18 @@ config MAINBOARD_DIR
 config MAINBOARD_FAMILY
 	string
 	default "Librem Mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2
+	default "Librem 14" if BOARD_PURISM_LIBREM_14
 
 config MAINBOARD_PART_NUMBER
 	string
 	default "Librem Mini" if BOARD_PURISM_LIBREM_MINI
 	default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2
+	default "Librem 14" if BOARD_PURISM_LIBREM_14
 
 config VARIANT_DIR
 	string
 	default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2
+	default "librem_14" if BOARD_PURISM_LIBREM_14
 
 config DEVICETREE
 	string
@@ -39,6 +42,7 @@ config CBFS_SIZE
 	hex
 	default 0x800000 if BOARD_PURISM_LIBREM_MINI
 	default 0xA00000 if BOARD_PURISM_LIBREM_MINI_V2
+	default 0x900000 if BOARD_PURISM_LIBREM_14
 
 config DIMM_MAX
 	int
@@ -51,7 +55,7 @@ config DIMM_SPD_SIZE
 config VGA_BIOS_ID
 	string
 	default "8086,3ea0" if BOARD_PURISM_LIBREM_MINI
-	default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2
+	default "8086,9b41" if BOARD_PURISM_LIBREM_MINI_V2 || BOARD_PURISM_LIBREM_14
 
 config PXE_ROM_ID
 	string
diff --git a/src/mainboard/purism/librem_cnl/Kconfig.name b/src/mainboard/purism/librem_cnl/Kconfig.name
index 1d10e791f1..5a2b3c2c1e 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig.name
+++ b/src/mainboard/purism/librem_cnl/Kconfig.name
@@ -7,3 +7,14 @@ config BOARD_PURISM_LIBREM_MINI_V2
 	bool "Librem Mini v2"
 	select BOARD_PURISM_BASEBOARD_LIBREM_CNL
 	select SOC_INTEL_COMETLAKE_1
+
+config BOARD_PURISM_LIBREM_14
+	bool "Librem 14"
+	select BOARD_PURISM_BASEBOARD_LIBREM_CNL
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM1
+	select SOC_INTEL_COMETLAKE_1
+	select SYSTEM_TYPE_LAPTOP
diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc
index c8cfa2212e..131385e255 100644
--- a/src/mainboard/purism/librem_cnl/Makefile.inc
+++ b/src/mainboard/purism/librem_cnl/Makefile.inc
@@ -5,6 +5,7 @@ romstage-y += variants/$(VARIANT_DIR)/variant.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt b/src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt
new file mode 100644
index 0000000000..d9cc69d93d
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Purism
+Board name: Librem 14
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/data.vbt b/src/mainboard/purism/librem_cnl/variants/librem_14/data.vbt
new file mode 100644
index 0000000000..e1943f832e
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/data.vbt
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
new file mode 100644
index 0000000000..dc89bd4263
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
@@ -0,0 +1,284 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		/* Touchpad */
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 20,
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+	}"
+
+	# Acoustic Noise
+	register "AcousticNoiseMitigation" = "1"
+
+	register "FastPkgCRampDisableIa" = "1"
+	register "FastPkgCRampDisableGt" = "1"
+	register "FastPkgCRampDisableSa" = "1"
+	register "FastPkgCRampDisableFivr" = "1"
+
+	register "SlowSlewRateForIa" = "3"	# fast/16
+	register "SlowSlewRateForGt" = "3"	# fast/16
+	register "SlowSlewRateForSa" = "2"	# fast/8
+	register "SlowSlewRateForFivr" = "3"	# fast/16
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3"	# 50ms
+	register "PchPmSlpS4MinAssert" = "1"	# 1s
+	register "PchPmSlpSusMinAssert" = "2"	# 500ms
+	register "PchPmSlpAMinAssert" = "4"	# 2s
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_C"
+	register "gpe0_dw1" = "PMC_GPP_D"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on	# Integrated Graphics Device
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+			register "panel_cfg" = "{
+				.up_delay_ms		=  200,
+				.down_delay_ms		=   50,
+				.cycle_delay_ms		=  500,
+				.backlight_pwm_hz	= 1000,
+				.backlight_on_delay_ms	=    1,
+				.backlight_off_delay_ms	=    1,
+			}"
+		end
+		device pci 04.0 on	# SA Thermal device
+			register "Device4Enable" = "1"
+		end
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on	# USB xHCI
+			chip drivers/usb/acpi
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-A Port""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(0, 0)"
+						device usb 2.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.2 on end
+					end
+					chip drivers/usb/acpi
+						device usb 2.3 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.4 off end
+					end
+					chip drivers/usb/acpi
+						device usb 2.5 off end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-A Port""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 0)"
+						device usb 2.6 off end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(0, 1)"
+						device usb 2.7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device usb 2.8 on end
+					end
+					chip drivers/usb/acpi
+						device usb 2.9 off end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-A Port""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(0, 0)"
+						device usb 3.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-A Port""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 0)"
+						device usb 3.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Right Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(0, 1)"
+						device usb 3.2 off end
+					end
+					chip drivers/usb/acpi
+						device usb 3.3 off end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Left Type-C Port""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device usb 3.4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Card Reader""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.5 on end
+					end
+				end
+			end
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-A right
+			register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)"	# Webcam
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# m.2-2230/Bluetooth
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"		# Type-A left
+			register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C right
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C left
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A right
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A left
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C right
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C left
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Card Reader
+		end
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 15.0 on	# I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid" = ""HTIX5288""
+				register "generic.name" = ""TPD0""
+				register "generic.uid" = "1"
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B20_IRQ)"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on	# SATA
+			register "SataMode" = "SATA_AHCI"
+			register "satapwroptimize" = "1"
+			register "SataSalpSupport" = "1"
+			# Port 2 (M.2 / inner)
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+			# Port 3 (M.2 / outer)
+			register "SataPortsEnable[2]" = "1"
+			register "SataPortsDevSlp[2]" = "1"
+		end
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 off end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 on	# PCI Express Port 7 -- x1 M.2/E 2230 (WLAN)
+			register "PcieRpEnable[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpLtrEnable[6]" = "1"
+			register "PcieRpHotPlug[6]" = "1"
+			register "PcieClkSrcUsage[2]" = "6"
+			register "PcieClkSrcClkReq[2]" = "2"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
+		end
+		device pci 1c.7 on	# PCI Express Port 8 -- x1 (LAN)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieClkSrcUsage[3]" = "7"
+			register "PcieClkSrcClkReq[3]" = "3"
+		end
+		device pci 1d.0 on	# PCI Express Port 9 -- x4 M.2/M 2280 (NVMe)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[0]" = "8"
+			register "PcieClkSrcClkReq[0]" = "0"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on	# PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
+			register "PcieRpEnable[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpLtrEnable[12]" = "1"
+			register "PcieClkSrcUsage[1]" = "12"
+			register "PcieClkSrcClkReq[1]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on	# LPC Bridge
+			# LPC configuration from lspci -s 1f.0 -xxx
+			# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
+			register "gen1_dec" = "0x00040069"
+			# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+			register "gen2_dec" = "0x00fc0e01"
+			# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+			register "gen3_dec" = "0x00fc0f01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on  end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on	# Intel HDA
+			register "PchHdaAudioLinkHda" = "1"
+		end
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/gma-mainboard.ads b/src/mainboard/purism/librem_cnl/variants/librem_14/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c
new file mode 100644
index 0000000000..49c6b8a767
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c
@@ -0,0 +1,600 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../../variant.h"
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - RCIN# */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+
+	/* GPP_A1 - LAD0 */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+
+	/* GPP_A2 - LAD1 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+
+	/* GPP_A3 - LAD2 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+
+	/* GPP_A4 - LAD3 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+
+	/* GPP_A5 - LFRAME# */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+
+	/* GPP_A6 - SERIRQ */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+
+	/* GPP_A7 - TPM_SPI_PIRQ# */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+
+	/* GPP_A8 - CLKRUN# */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+
+	/* GPP_A9 - CLKOUT_LPC0 */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+
+	/* GPP_A10 - CLKOUT_LPC1 */
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+
+	/* GPP_A11 - NC */
+	PAD_NC(GPP_A11, UP_20K),
+
+	/* GPP_A12 - NC */
+	PAD_NC(GPP_A12, UP_20K),
+
+	/* GPP_A13 - NC */
+	PAD_NC(GPP_A13, NONE),
+
+	/* GPP_A14 - SUS_STAT# */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+
+	/* GPP_A15 - NC */
+	PAD_NC(GPP_A15, NONE),
+
+	/* GPP_A16 - NC */
+	PAD_NC(GPP_A16, UP_20K),
+
+	/* GPP_A17 - NC */
+	PAD_NC(GPP_A17, NONE),
+
+	/* GPP_A18 - NC */
+	PAD_NC(GPP_A18, NONE),
+
+	/* GPP_A19 - NC */
+	PAD_NC(GPP_A19, NONE),
+
+	/* GPP_A20 - NC */
+	PAD_NC(GPP_A20, NONE),
+
+	/* GPP_A21 - NC */
+	PAD_NC(GPP_A21, UP_20K),
+
+	/* GPP_A22 - NC */
+	PAD_NC(GPP_A22, UP_20K),
+
+	/* GPP_A23 - NC */
+	PAD_NC(GPP_A23, UP_20K),
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_B0 - CORE_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+	/* GPP_B1 - CORE_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+	/* GPP_B2 - VRALERT# */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),
+
+	/* GPP_B3 - NC */
+	PAD_NC(GPP_B3, NONE),
+
+	/* GPP_B4 - NC */
+	PAD_NC(GPP_B4, UP_20K),
+
+	/* GPP_B5 - SRCCLKREQ0# / SSD1 */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+
+	/* GPP_B6 - SRCCLKREQ1# / SSD0 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+
+	/* GPP_B8 - SRCCLKREQ2# / WIFI */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+
+	/* GPP_B8 - SRCCLKREQ3# / LAN */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+
+	/* GPP_B9 - NC */
+	PAD_NC(GPP_B9, UP_20K),
+
+	/* GPP_B10 - NC */
+	PAD_NC(GPP_B10, UP_20K),
+
+	/* GPP_B11 - NC */
+	PAD_NC(GPP_B11, NONE),
+
+	/* GPP_B12 - SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+	/* GPP_B13 - PLTRST# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	/* GPP_B14 - NC */
+	PAD_NC(GPP_B14, NONE),
+
+	/* GPP_B15 - NC */
+	PAD_NC(GPP_B15, NONE),
+
+	/* GPP_B16 - LAN_RST */
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+
+	/* GPP_B17 - WLAN_PCIE_RST */
+	PAD_CFG_GPO(GPP_B17, 0, PLTRST),
+
+	/* GPP_B18 - NC */
+	PAD_NC(GPP_B18, NONE),
+
+	/* GPP_B19 - USB3_P1_PWREN */
+	PAD_CFG_GPO(GPP_B19, 1, PLTRST),
+
+	/* GPP_B20 - TP_INT#
+	 *
+	 * Due to interrupts failing to trigger when correctly configured
+	 * active-low as PAD_CFG_GPI_APIC_LOW(GPP_B20, NONE, PLTRST),
+	 * must configure instead as active-high:
+	 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, LEVEL, ACPI),
+
+	/* GPP_B21 - NC */
+	PAD_NC(GPP_B21, UP_20K),
+
+	/* GPP_B22 - NC */
+	PAD_NC(GPP_B22, NONE),
+
+	/* GPP_B23 - NC */
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Group GPP_G ------- */
+
+	/* GPP_G0 - NC */
+	PAD_NC(GPP_G0, NONE),
+
+	/* GPP_G1 - NC */
+	PAD_NC(GPP_G1, NONE),
+
+	/* GPP_G2 - NC */
+	PAD_NC(GPP_G2, NONE),
+
+	/* GPP_G3 - NC */
+	PAD_NC(GPP_G3, NONE),
+
+	/* GPP_G4 - NC */
+	PAD_NC(GPP_G4, NONE),
+
+	/* GPP_G5 - NC */
+	PAD_NC(GPP_G5, UP_20K),
+
+	/* GPP_G6 - NC */
+	PAD_NC(GPP_G6, NONE),
+
+	/* GPP_G7 - NC */
+	PAD_NC(GPP_G7, DN_20K),
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* GPP_D0 - NC */
+	PAD_NC(GPP_D0, UP_20K),
+
+	/* GPP_D1 - NC */
+	PAD_NC(GPP_D1, UP_20K),
+
+	/* GPP_D2 - NC */
+	PAD_NC(GPP_D2, UP_20K),
+
+	/* GPP_D3 - NC */
+	PAD_NC(GPP_D3, UP_20K),
+
+	/* GPP_D4 - NC */
+	PAD_NC(GPP_D4, UP_20K),
+
+	/* GPP_D5 - ISH_I2C0_SDA */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+
+	/* GPP_D6 - ISH_I2C0_SCL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+
+	/* GPP_D7 - PCH_NVME_RST */
+	PAD_CFG_GPO(GPP_D7, 1, PLTRST),
+
+	/* GPP_D8 - PCH_NVME_RST1 */
+	PAD_CFG_GPO(GPP_D8, 1, PLTRST),
+
+	/* GPP_D9 - TP_RST */
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+
+	/* GPP_D10 - NC */
+	PAD_NC(GPP_D10, NONE),
+
+	/* GPP_D11 - NC */
+	PAD_NC(GPP_D11, UP_20K),
+
+	/* GPP_D12 - NC */
+	PAD_NC(GPP_D12, UP_20K),
+
+	/* GPP_D13 - NC */
+	PAD_NC(GPP_D13, NONE),
+
+	/* GPP_D14 - NC */
+	PAD_NC(GPP_D14, UP_20K),
+
+	/* GPP_D15 - NC */
+	PAD_NC(GPP_D15, UP_20K),
+
+	/* GPP_D16 - NC */
+	PAD_NC(GPP_D16, UP_20K),
+
+	/* GPP_D17 - DMIC_CLK1 */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+
+	/* GPP_D18 - DMIC_DATA1 */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+
+	/* GPP_D19 - DMIC_CLK0 */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* GPP_D20 - DMIC_DATA0 */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* GPP_D21 - NC */
+	PAD_NC(GPP_D21, UP_20K),
+
+	/* GPP_D22 - NC */
+	PAD_NC(GPP_D22, UP_20K),
+
+	/* GPP_D23 - NC */
+	PAD_NC(GPP_D23, UP_20K),
+
+	/* ------- GPIO Group GPP_F ------- */
+
+	/* GPP_F0 - NC */
+	PAD_NC(GPP_F0, NONE),
+
+	/* GPP_F1 - NC */
+	PAD_NC(GPP_F1, UP_20K),
+
+	/* GPP_F2 - NC */
+	PAD_NC(GPP_F2, UP_20K),
+
+	/* GPP_F3 - NC */
+	PAD_NC(GPP_F3, UP_20K),
+
+	/* GPP_F4 - NC */
+	PAD_NC(GPP_F4, UP_20K),
+
+	/* GPP_F5 - NC */
+	PAD_NC(GPP_F5, UP_20K),
+
+	/* GPP_F6 - NC */
+	PAD_NC(GPP_F6, NONE),
+
+	/* GPP_F7 - NC */
+	PAD_NC(GPP_F7, NONE),
+
+	/* GPP_F8 - NC */
+	PAD_NC(GPP_F8, NONE),
+
+	/* GPP_F9 - NC */
+	PAD_NC(GPP_F9, NONE),
+
+	/* GPP_F10 - NC */
+	PAD_NC(GPP_F10, UP_20K),
+
+	/* GPP_F11 - NC */
+	PAD_NC(GPP_F11, UP_20K),
+
+	/* GPP_F12 - NC */
+	PAD_NC(GPP_F12, UP_20K),
+
+	/* GPP_F13 - NC */
+	PAD_NC(GPP_F13, UP_20K),
+
+	/* GPP_F14 - NC */
+	PAD_NC(GPP_F14, UP_20K),
+
+	/* GPP_F15 - NC */
+	PAD_NC(GPP_F15, UP_20K),
+
+	/* GPP_F16 - NC */
+	PAD_NC(GPP_F16, UP_20K),
+
+	/* GPP_F17 - NC */
+	PAD_NC(GPP_F17, UP_20K),
+
+	/* GPP_F18 - NC */
+	PAD_NC(GPP_F18, UP_20K),
+
+	/* GPP_F19 - NC */
+	PAD_NC(GPP_F19, UP_20K),
+
+	/* GPP_F20 - NC */
+	PAD_NC(GPP_F20, UP_20K),
+
+	/* GPP_F21 - NC */
+	PAD_NC(GPP_F21, UP_20K),
+
+	/* GPP_F22 - NC */
+	PAD_NC(GPP_F22, UP_20K),
+
+	/* GPP_F23 - NC */
+	PAD_NC(GPP_F23, UP_20K),
+
+	/* ------- GPIO Group GPP_H ------- */
+
+	/* GPP_H0 - M.2_BT_PCMCLK */
+	PAD_NC(GPP_H0, UP_20K),
+
+	/* GPP_H1 - M.2_BT_PCMSYNC */
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
+
+	/* GPP_H2 - M.2_BT_PCMOUT */
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
+
+	/* GPP_H3 - M.2_BT_PCMIN */
+	PAD_CFG_GPO(GPP_H3, 1, PLTRST),
+
+	/* GPP_H4 - NC */
+	PAD_NC(GPP_H4, NONE),
+
+	/* GPP_H5 - NC */
+	PAD_NC(GPP_H5, NONE),
+
+	/* GPP_H6 - NC */
+	PAD_NC(GPP_H6, UP_20K),
+
+	/* GPP_H7 - NC */
+	PAD_NC(GPP_H7, NONE),
+
+	/* GPP_H8 - NC */
+	PAD_NC(GPP_H8, NONE),
+
+	/* GPP_H9 - NC */
+	PAD_NC(GPP_H9, NONE),
+
+	/* GPP_H10 - NC */
+	PAD_NC(GPP_H10, NONE),
+
+	/* GPP_H11 - NC */
+	PAD_NC(GPP_H11, NONE),
+
+	/* GPP_H12 - NC */
+	PAD_NC(GPP_H12, UP_20K),
+
+	/* GPP_H13 - NC */
+	PAD_NC(GPP_H13, UP_20K),
+
+	/* GPP_H14 - NC */
+	PAD_NC(GPP_H14, UP_20K),
+
+	/* GPP_H15 - NC */
+	PAD_NC(GPP_H15, UP_20K),
+
+	/* GPP_H16 - NC */
+	PAD_NC(GPP_H16, UP_20K),
+
+	/* GPP_H17 - NC */
+	PAD_NC(GPP_H17, NONE),
+
+	/* GPP_H18 - CPU_C10_GATE# */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	/* GPP_H19 - NC */
+	PAD_NC(GPP_H19, UP_20K),
+
+	/* GPP_H20 - NC */
+	PAD_NC(GPP_H20, UP_20K),
+
+	/* GPP_H21 - NC */
+	PAD_NC(GPP_H21, NONE),
+
+	/* GPP_H22 - NC */
+	PAD_NC(GPP_H22, UP_20K),
+
+	/* GPP_H23 - NC */
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPD ------- */
+
+	/* GPD0 - BATLOW# */
+	PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),
+
+	/* GPD1 - ACPRESENT */
+	PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1),
+
+	/* GPD2 - LAN_WAKE# */
+	PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1),
+
+	/* GPD3 - PRWBTN# */
+	PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1),
+
+	/* GPD4 - SLP_S3# */
+	PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),
+
+	/* GPD5 - SLP_S4# */
+	PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),
+
+	/* GPD6 - SLP_A# */
+	PAD_CFG_NF(GPD6, NONE, RSMRST, NF1),
+
+	/* GPD7 - NC */
+	PAD_NC(GPD7, NONE),
+
+	/* GPD8 - SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),
+
+	/* GPD9 - SLP_WLAN# */
+	PAD_CFG_NF(GPD9, NONE, RSMRST, NF1),
+
+	/* GPD10 - SLP_S5# */
+	PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),
+
+	/* GPD11 - LANPHYPC */
+	PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+
+	/* GPP_C1 - SMBDATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* GPP_C2 - NC */
+	PAD_NC(GPP_C2, NONE),
+
+	/* GPP_C3 - SML0CLK */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+
+	/* GPP_C4 - SML0DATA */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+
+	/* GPP_C5 - NC */
+	PAD_NC(GPP_C5, NONE),
+
+	/* GPP_C6 - NC */
+	PAD_NC(GPP_C6, NONE),
+
+	/* GPP_C7 - NC */
+	PAD_NC(GPP_C7, NONE),
+
+	/* GPP_C8 - NC */
+	PAD_NC(GPP_C8, NONE),
+
+	/* GPP_C9 - NC */
+	PAD_NC(GPP_C9, NONE),
+
+	/* GPP_C10 - NC */
+	PAD_NC(GPP_C10, UP_20K),
+
+	/* GPP_C11 - NC */
+	PAD_NC(GPP_C11, UP_20K),
+
+	/* GPP_C12 - NC */
+	PAD_NC(GPP_C12, UP_20K),
+
+	/* GPP_C13 - NC */
+	PAD_NC(GPP_C13, UP_20K),
+
+	/* GPP_C14 - NC */
+	PAD_NC(GPP_C14, UP_20K),
+
+	/* GPP_C15 - NC */
+	PAD_NC(GPP_C15, UP_20K),
+
+	/* GPP_C16 - I2C0_SDA - TP */
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+
+	/* GPP_C17 - I2C0_SCL - TP */
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+
+	/* GPP_C18 - NC */
+	PAD_NC(GPP_C18, UP_20K),
+
+	/* GPP_C19 - NC */
+	PAD_NC(GPP_C19, UP_20K),
+
+	/* GPP_C20 - NC */
+	PAD_NC(GPP_C20, NONE),
+
+	/* GPP_C21 - NC */
+	PAD_NC(GPP_C21, NONE),
+
+	/* GPP_C22 - NC */
+	PAD_NC(GPP_C22, NONE),
+
+	/* GPP_C23 - NC */
+	PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E0 - NC */
+	PAD_NC(GPP_E0, UP_20K),
+
+	/* GPP_E1 - SATAXPCIE1 */
+	PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1),
+
+	/* GPP_E2 - SATAXPCIE2 */
+	PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1),
+
+	/* GPP_E3 - NC */
+	PAD_NC(GPP_E3, NONE),
+
+	/* GPP_E4 - SATA_DEVSLP0 */
+	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+
+	/* GPP_E5 - SATA_DEVSLP1 */
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+
+	/* GPP_E6 - NC */
+	PAD_NC(GPP_E6, UP_20K),
+
+	/* GPP_E7 - NC */
+	PAD_NC(GPP_E7, NONE),
+
+	/* GPP_E8 - NC */
+	PAD_NC(GPP_E8, UP_20K),
+
+	/* GPP_E9 - USB2_OC0# */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+
+	/* GPP_E10 - USB2_OC1# */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+
+	/* GPP_E11 - USB2_OC2# */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+
+	/* GPP_E12 - NC */
+	PAD_NC(GPP_E12, NONE),
+
+	/* GPP_E13 - DDPB_HPD0 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+	/* GPP_E14 - DDPC_HPD1 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* GPP_E15 - SMC_EXTSMI# */
+	PAD_CFG_GPI_SCI_LOW(GPP_E15, UP_20K, PLTRST, LEVEL),
+
+	/* GPP_E16 - SMC_RUNTIME_SCI# */
+	PAD_CFG_GPI_SCI_LOW(GPP_E16, UP_20K, PLTRST, LEVEL),
+
+	/* GPP_E17 - EDP_HPD */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+
+	/* GPP_E18 - NC */
+	PAD_NC(GPP_E18, UP_20K),
+
+	/* GPP_E19 - NC */
+	PAD_NC(GPP_E19, NONE),
+
+	/* GPP_E20 - NC */
+	PAD_NC(GPP_E20, NONE),
+
+	/* GPP_E21 - NC */
+	PAD_NC(GPP_E21, NONE),
+
+	/* GPP_E22 - NC */
+	PAD_NC(GPP_E22, UP_20K),
+
+	/* GPP_E23 - NC */
+	PAD_NC(GPP_E23, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
new file mode 100644
index 0000000000..97422ef317
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0256,	/* Codec Vendor/Device ID: Realtek ALC256 */
+	0x1b50580a,	/* Subsystem ID */
+	12,		/* Number of entries */
+
+	AZALIA_SUBVENDOR(0, 0x1b50580a),
+
+	/* Widget node 0x01 */
+	0x0017ff00,
+	0x0017ff00,
+	0x0017ff00,
+	0x0017ff00,
+
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140), /* Front digital mic */
+	AZALIA_PIN_CFG(0, 0x13, 0x411111f0), /* NC */
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Internal speakers */
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0), /* NC */
+	AZALIA_PIN_CFG(0, 0x19, 0x04a11030), /* Jack analog mic */
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* NC */
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* NC */
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), /* NC */
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* NC */
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020), /* Jack analog out */
+
+	/* Hidden SW reset */
+	0x0205001a,
+	0x0204c003,
+	0x0205001a,
+	0x02048003,
+
+	/* Class D power on reset control */
+	0x0205003c,
+	0x02040354,
+	0x0205003c,
+	0x02040314,
+
+	/* LDO3 output set to 1.2V */
+	0x0205001b,
+	0x02040a4b,
+	0x02050019,
+	0x02040e12,
+
+	/* SPK power */
+	0x02050038,
+	0x02046901,
+	0x02050007,
+	0x02040200,
+
+	0x8086280b,	/* Codec Vendor/Device ID: Intel CometPoint HDMI */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of entries */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl
new file mode 100644
index 0000000000..611643b54a
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_E15 SWI
+Method (_L49, 0, Serialized) {
+	Debug = Concatenate("GPE _L49: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl
new file mode 100644
index 0000000000..48c50e075e
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/sleep.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl
new file mode 100644
index 0000000000..def6ee0b8e
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/variant.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SWI 0x49 /* GPP_E15 */
+#define EC_GPE_SCI 0x50 /* GPP_E16 */
+#define EC_COLOR_KEYBOARD 0
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}
+
+Scope (\_SB.PCI0)
+{
+	#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+}
+
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/pc/ps2_controller.asl>
+}
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/variant.c b/src/mainboard/purism/librem_cnl/variants/librem_14/variant.c
new file mode 100644
index 0000000000..33f5b6a5ef
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/variant.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../../variant.h"
+
+void variant_memory_init_params(FSP_M_CONFIG *mem_cfg)
+{
+	/* No SATA HSIO adjustments needed currently */
+}