diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-18 19:11:24 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 21:22:43 +0100 |
| commit | 4cb44e564530fd1fc73f809542f8dbebf79f1c1a (patch) | |
| tree | c36a3c0be88734176c5925b42ef01cba7437a674 | |
| parent | fc5d85cc66046b239fdd45ff422d70146da1030c (diff) | |
| download | coreboot-4cb44e564530fd1fc73f809542f8dbebf79f1c1a.tar.xz | |
intel sandy/ivy: Move SPD loading after TS_BEFORE_INITRAM
Take the timestamp before SPD loading takes place, for easier
comparison against MRC blob performance and followup changes
will optimize some of the slow SPD/SMBus operations.
Change-Id: I50b5a9d02d2caf4c63e1a4025544131a085b8fb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17489
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.h | 1 |
2 files changed, 6 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6ae253dbfe..c01bc253db 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -4180,13 +4180,13 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, return 0; } -void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, - int s3resume) +static void init_dram_ddr3(int mobile, int min_tck, int s3resume) { int me_uma_size; int cbmem_was_inited; ramctr_timing ctrl; int fast_boot; + spd_raw_data spds[4]; struct mrc_data_container *mrc_cache; ramctr_timing *ctrl_cached; int err; @@ -4235,6 +4235,9 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; } + memset(spds, 0, sizeof(spds)); + mainboard_get_spd(spds); + /* verify MRC cache for fast boot */ if (ctrl_cached) { /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ @@ -4412,14 +4415,9 @@ static unsigned int get_mmio_size(void) void perform_raminit(int s3resume) { - spd_raw_data spd[4]; - post_code(0x3a); - memset (spd, 0, sizeof(spd)); - mainboard_get_spd(spd); - timestamp_add_now(TS_BEFORE_INITRAM); - init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); + init_dram_ddr3(1, get_mem_min_tck(), s3resume); } diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index 8f8d057313..0b26bd9b30 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -20,7 +20,6 @@ #include <device/dram/ddr3.h> /* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB. */ -void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, int s3resume); void read_spd(spd_raw_data *spd, u8 addr); void mainboard_get_spd(spd_raw_data *spd); |