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authorUwe Hermann <uwe@hermann-uwe.de>2009-04-11 13:59:00 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2009-04-11 13:59:00 +0000
commit4eb37059cea9ad4fae2f959dc023f6537f722717 (patch)
treea54346c630f68482f4d1b56b8a2cb7c2a8198b8e
parent1da9a79a069a85c05314ca33b53f6c1b0d98d733 (diff)
downloadcoreboot-4eb37059cea9ad4fae2f959dc023f6537f722717.tar.xz
Mention a few more flash chip packages in README/manpage.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--util/flashrom/README5
-rw-r--r--util/flashrom/flashrom.89
2 files changed, 8 insertions, 6 deletions
diff --git a/util/flashrom/README b/util/flashrom/README
index a4eee499dd..2d26877006 100644
--- a/util/flashrom/README
+++ b/util/flashrom/README
@@ -5,8 +5,9 @@ Flashrom README
Flashrom is a utility for reading, writing, and erasing flash ROM chips.
It's often used to flash BIOS/coreboot/firmware images.
-It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
-various protocols such as LPC, FWH, parallel flash, or SPI.
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
+TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
+or SPI.
(see http://coreboot.org for details on coreboot)
diff --git a/util/flashrom/flashrom.8 b/util/flashrom/flashrom.8
index d732e1acb3..cf6f5fd50e 100644
--- a/util/flashrom/flashrom.8
+++ b/util/flashrom/flashrom.8
@@ -1,6 +1,6 @@
-.TH FLASHROM 8 "January 5, 2009"
+.TH FLASHROM 8 "April 11, 2009"
.SH NAME
-flashrom \- utility for reading, writing, and erasing BIOS/ROM/flash chips
+flashrom \- read, write, and erase BIOS/ROM/flash chips
.SH SYNOPSIS
.B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end]
[\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file]
@@ -9,8 +9,9 @@ flashrom \- utility for reading, writing, and erasing BIOS/ROM/flash chips
is a utility for reading, writing, and erasing flash ROM chips.
It's often used to flash BIOS/coreboot/firmware images.
.PP
-It supports a wide range of DIP32, PLCC32, DIP8, and TSOP chips, which use
-various protocols such as LPC, FWH, parallel flash, or SPI.
+It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
+TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
+or SPI.
.PP
(see
.B http://coreboot.org