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authorMarc Jones <marcj303@gmail.com>2018-08-01 12:45:03 -0600
committerMartin Roth <martinroth@google.com>2018-08-06 16:37:06 +0000
commit509e5fd4c0d2da06bd7f413e01db1c094156206f (patch)
tree4ef5ba752aeb42a670c795a45ae102085c6988da
parent2b26baa625baab2f60a480c4f48918425bf3bb1d (diff)
downloadcoreboot-509e5fd4c0d2da06bd7f413e01db1c094156206f.tar.xz
soc/amd/stoneyridge: Call AMD ALIB method with AC/DC state
AMD ALIB Function 1 accepts the AC/DC startup state. This is reported to be required for AMD PSPP settings. BUG=b:112020107 TEST= build test Change-Id: Ibb6c872d84745217912956c15d6ca2e8ba387561 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27785 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index 81964baa48..2855b23fab 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -14,6 +14,8 @@
* GNU General Public License for more details.
*/
+External(\_SB.ALIB, MethodObj)
+
/* System Bus */
/* _SB.PCI0 */
@@ -138,7 +140,7 @@ Method(_CRS, 0) {
* 2. Get PCI Interrupt routing from ACPI VSM, this
* value is based on user choice in BIOS setup.
*/
-Method(_INI, 0) {
+Method(_INI, 0, Serialized) {
/* DBGO("\\_SB\\_INI\n") */
/* DBGO(" DSDT.ASL code from ") */
/* DBGO(__DATE__) */
@@ -154,6 +156,17 @@ Method(_INI, 0) {
/* Determine the OS we're running on */
OSFL()
+
+ /* Send ALIB Function 1 the AC/DC state */
+ Name(F1BF, Buffer(0x03){})
+ CreateWordField(F1BF, 0, F1SZ)
+ CreateByteField(F1BF, 2, F1DA)
+
+ Store(3, F1SZ)
+ Store(\PWRS, F1DA)
+
+ \_SB.ALIB(1, F1BF)
+
} /* End Method(_SB._INI) */
Method(OSFL, 0){