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authorLijian Zhao <lijian.zhao@intel.com>2018-03-19 17:13:48 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-03-22 09:00:48 +0000
commit5479525c74ce301754aee8a0955f258bdb751614 (patch)
tree57c337279300cdbb92db231f755122ffe4eb1c3b
parenta3ad990089ec0a13df52c7451ee5092229346bf6 (diff)
downloadcoreboot-5479525c74ce301754aee8a0955f258bdb751614.tar.xz
intel/fsp: Update Cannonlake FSP header
Update Cannonlake FSP header to version 7.x.2A.20, the following changes were made: 1. Add MemtestonWarmBoot option. 2. Add enable8254clockgatingonS3 option. 3. Default disable Tccoffsetlock BUG=None TEST=None Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h10
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h18
2 files changed, 21 insertions, 7 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
index d014f81bf9..74cc6728b7 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
@@ -2291,9 +2291,15 @@ typedef struct {
**/
UINT8 PegImrRpSelection;
-/** Offset 0x0513
+/** Offset 0x0513 - Memory Test on Warm Boot
+ Run Base Memory Test on Warm Boot
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemTestOnWarmBoot;
+
+/** Offset 0x0514
**/
- UINT8 ReservedFspmUpd[12];
+ UINT8 ReservedFspmUpd[11];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index 0f3577ae32..4daf8915c9 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -2154,9 +2154,17 @@ typedef struct {
**/
UINT8 SataRstCpuAttachedStorage;
-/** Offset 0x0752
+/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+ avoids the SMI requirement for the programming.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGatingOnS3;
+
+/** Offset 0x0753
**/
- UINT8 UnusedUpdSpace25[2];
+ UINT8 UnusedUpdSpace25;
/** Offset 0x0754 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -2472,7 +2480,7 @@ typedef struct {
/** Offset 0x07DA - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
- target; 0: Disabled; <b>1: Enabled </b>.
+ target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
@@ -2886,13 +2894,13 @@ typedef struct {
/** Offset 0x0870 - Package PL4 power limit
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
+ Range 0 to 1023875 in Step size of 125
**/
UINT32 PowerLimit4;
/** Offset 0x0874 - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
+ Range 0 to 1023875 in Step size of 125
**/
UINT32 TccOffsetTimeWindowForRatl;