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authorLijian Zhao <lijian.zhao@intel.com>2018-06-15 15:50:32 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-07-02 07:27:31 +0000
commit58f68e80ec5f9f3d5cf65d6b9360030109b420e0 (patch)
tree0eea01093e4785b64ce5c99a24afb995a2ce0621
parente78af973499d906c8cc27b2515148b4a8494d35a (diff)
downloadcoreboot-58f68e80ec5f9f3d5cf65d6b9360030109b420e0.tar.xz
mainboard/google/nocturne: Enable IPU3
Enable Image Processing Unit and CIO2 device that constitute IPU3. BUG=None TEST=Build and boot up into Nocturne platform and check with lspci. Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 17bd3c0eb4..d8151431e4 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -40,8 +40,8 @@ chip soc/intel/skylake
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
- register "Cio2Enable" = "0" # FIXME: enable once MIPI is ready
- register "SaImguEnable" = "0" # FIXME: enable once MIPI is ready
+ register "Cio2Enable" = "1"
+ register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"