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authormarxwang <marx.wang@intel.com>2018-09-11 12:08:23 +0800
committerMartin Roth <martinroth@google.com>2018-09-21 14:30:52 +0000
commit5b5656565ba4046f7d7fdc61d9fc79a1f67993be (patch)
treefddb6f6e5e3969c1f5a48deda8a027e02ccdea89
parenteaca95eaf4cf074818e8e1bfa18f0b137143cc89 (diff)
downloadcoreboot-5b5656565ba4046f7d7fdc61d9fc79a1f67993be.tar.xz
mb/google/poppy/variants/rammus: Disable command TriState for rammus
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL. BUG=none TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28568 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 3478744137..7b851ac811 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -27,6 +27,9 @@ chip soc/intel/skylake
# Enable S0ix
register "s0ix_enable" = "1"
+ # Disable Command TriState
+ register "CmdTriStateDis" = "1"
+
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"